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733a87783c
This introduces a new file, RISCVISAUtils.cpp and moves the rest of RISCVISAInfo to the TargetParser library. This will allow us to generate part of RISCVISAInfo.cpp using tablegen.
106 lines
3.7 KiB
C++
106 lines
3.7 KiB
C++
//===- RISCVTargetDefEmitter.cpp - Generate lists of RISC-V CPUs ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This tablegen backend emits the include file needed by the target
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// parser to parse the RISC-V CPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/RISCVISAUtils.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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using namespace llvm;
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// We can generate march string from target features as what has been described
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// in RISC-V ISA specification (version 20191213) 'Chapter 27. ISA Extension
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// Naming Conventions'.
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//
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// This is almost the same as RISCVFeatures::parseFeatureBits, except that we
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// get feature name from feature records instead of feature bits.
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static void printMArch(raw_ostream &OS, const Record &Rec) {
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std::map<std::string, RISCVISAUtils::ExtensionVersion,
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RISCVISAUtils::ExtensionComparator>
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Extensions;
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unsigned XLen = 0;
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// Convert features to FeatureVector.
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for (auto *Feature : Rec.getValueAsListOfDefs("Features")) {
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StringRef FeatureName = Feature->getValueAsString("Name");
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if (Feature->isSubClassOf("RISCVExtension")) {
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unsigned Major = Feature->getValueAsInt("MajorVersion");
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unsigned Minor = Feature->getValueAsInt("MinorVersion");
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Extensions[FeatureName.str()] = {Major, Minor};
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} else if (FeatureName == "64bit") {
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assert(XLen == 0 && "Already determined XLen");
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XLen = 64;
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} else if (FeatureName == "32bit") {
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assert(XLen == 0 && "Already determined XLen");
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XLen = 32;
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}
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}
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assert(XLen != 0 && "Unable to determine XLen");
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OS << "rv" << XLen;
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ListSeparator LS("_");
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for (auto const &Ext : Extensions)
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OS << LS << Ext.first << Ext.second.Major << 'p' << Ext.second.Minor;
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}
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static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) {
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OS << "#ifndef PROC\n"
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<< "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)\n"
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<< "#endif\n\n";
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// Iterate on all definition records.
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for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) {
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bool FastScalarUnalignedAccess =
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any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
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return Feature->getValueAsString("Name") == "unaligned-scalar-mem";
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});
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bool FastVectorUnalignedAccess =
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any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) {
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return Feature->getValueAsString("Name") == "unaligned-vector-mem";
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});
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bool FastUnalignedAccess =
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FastScalarUnalignedAccess && FastVectorUnalignedAccess;
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OS << "PROC(" << Rec->getName() << ", {\"" << Rec->getValueAsString("Name")
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<< "\"}, {\"";
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StringRef MArch = Rec->getValueAsString("DefaultMarch");
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// Compute MArch from features if we don't specify it.
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if (MArch.empty())
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printMArch(OS, *Rec);
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else
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OS << MArch;
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OS << "\"}, " << FastUnalignedAccess << ")\n";
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}
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OS << "\n#undef PROC\n";
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OS << "\n";
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OS << "#ifndef TUNE_PROC\n"
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<< "#define TUNE_PROC(ENUM, NAME)\n"
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<< "#endif\n\n";
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for (const Record *Rec :
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RK.getAllDerivedDefinitions("RISCVTuneProcessorModel")) {
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OS << "TUNE_PROC(" << Rec->getName() << ", "
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<< "\"" << Rec->getValueAsString("Name") << "\")\n";
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}
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OS << "\n#undef TUNE_PROC\n";
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}
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static TableGen::Emitter::Opt X("gen-riscv-target-def", EmitRISCVTargetDef,
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"Generate the list of CPU for RISCV");
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