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1df4af6cbc
Reapplies #134068. The first patch was missing a check to prevent attempts to pair SVE fill/spill with other Neon load/store instructions, which could happen specifically if the Neon instruction was unscaled.
284 lines
12 KiB
LLVM
284 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=aarch64_be-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s --check-prefixes=CHECK-BE
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve,ldp-aligned-only -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s --check-prefixes=CHECK-LDPALIGNEDONLY
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve,stp-aligned-only -aarch64-sve-vector-bits-min=128 -aarch64-sve-vector-bits-max=128 < %s | FileCheck %s --check-prefixes=CHECK-STPALIGNEDONLY
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK-OFF
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=256 -aarch64-sve-vector-bits-max=256 < %s | FileCheck %s --check-prefixes=CHECK-OFF
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define void @nxv16i8(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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;
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; CHECK-BE-LABEL: nxv16i8:
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; CHECK-BE: // %bb.0:
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; CHECK-BE-NEXT: ptrue p0.b
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; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0]
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; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, #1, mul vl]
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; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1]
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; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, #1, mul vl]
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; CHECK-BE-NEXT: ret
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;
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; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8:
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; CHECK-LDPALIGNEDONLY: // %bb.0:
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0]
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #1, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: stp q0, q1, [x1]
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; CHECK-LDPALIGNEDONLY-NEXT: ret
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;
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; CHECK-STPALIGNEDONLY-LABEL: nxv16i8:
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; CHECK-STPALIGNEDONLY: // %bb.0:
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; CHECK-STPALIGNEDONLY-NEXT: ldp q0, q1, [x0]
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; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1]
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; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #1, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: ret
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;
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; CHECK-OFF-LABEL: nxv16i8:
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; CHECK-OFF: // %bb.0:
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; CHECK-OFF-NEXT: ldr z0, [x0]
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; CHECK-OFF-NEXT: ldr z1, [x0, #1, mul vl]
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; CHECK-OFF-NEXT: str z0, [x1]
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; CHECK-OFF-NEXT: str z1, [x1, #1, mul vl]
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; CHECK-OFF-NEXT: ret
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%vscale = tail call i64 @llvm.vscale()
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%vl = shl nuw nsw i64 %vscale, 4
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%ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %vl
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%stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %vl
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%ld1 = load <vscale x 16 x i8>, ptr %ldptr, align 1
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%ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1
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store <vscale x 16 x i8> %ld1, ptr %stptr, align 1
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store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1
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ret void
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}
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define void @nxv16i8_max_range(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv16i8_max_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0, #-1024]
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; CHECK-NEXT: stp q0, q1, [x1, #1008]
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; CHECK-NEXT: ret
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;
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; CHECK-BE-LABEL: nxv16i8_max_range:
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; CHECK-BE: // %bb.0:
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; CHECK-BE-NEXT: rdvl x8, #1
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; CHECK-BE-NEXT: mov x9, #-1008 // =0xfffffffffffffc10
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; CHECK-BE-NEXT: mov x10, #-1024 // =0xfffffffffffffc00
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; CHECK-BE-NEXT: lsr x8, x8, #4
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; CHECK-BE-NEXT: mov w11, #1008 // =0x3f0
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; CHECK-BE-NEXT: mov w12, #1024 // =0x400
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; CHECK-BE-NEXT: ptrue p0.b
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; CHECK-BE-NEXT: mul x9, x8, x9
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; CHECK-BE-NEXT: mul x10, x8, x10
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; CHECK-BE-NEXT: mul x11, x8, x11
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; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, x9]
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; CHECK-BE-NEXT: mul x8, x8, x12
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; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0, x10]
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; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1, x11]
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; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, x8]
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; CHECK-BE-NEXT: ret
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;
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; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8_max_range:
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; CHECK-LDPALIGNEDONLY: // %bb.0:
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0, #-64, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #-63, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: stp q0, q1, [x1, #1008]
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; CHECK-LDPALIGNEDONLY-NEXT: ret
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;
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; CHECK-STPALIGNEDONLY-LABEL: nxv16i8_max_range:
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; CHECK-STPALIGNEDONLY: // %bb.0:
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; CHECK-STPALIGNEDONLY-NEXT: ldp q0, q1, [x0, #-1024]
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; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1, #63, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #64, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: ret
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;
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; CHECK-OFF-LABEL: nxv16i8_max_range:
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; CHECK-OFF: // %bb.0:
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; CHECK-OFF-NEXT: ldr z0, [x0, #-64, mul vl]
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; CHECK-OFF-NEXT: ldr z1, [x0, #-63, mul vl]
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; CHECK-OFF-NEXT: str z0, [x1, #63, mul vl]
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; CHECK-OFF-NEXT: str z1, [x1, #64, mul vl]
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; CHECK-OFF-NEXT: ret
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%vscale = tail call i64 @llvm.vscale()
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%ldoff1 = mul i64 %vscale, -1024
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%ldoff2 = mul i64 %vscale, -1008
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%stoff1 = mul i64 %vscale, 1008
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%stoff2 = mul i64 %vscale, 1024
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%ldptr1 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff1
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%ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff2
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%stptr1 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff1
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%stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff2
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%ld1 = load <vscale x 16 x i8>, ptr %ldptr1, align 1
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%ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1
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store <vscale x 16 x i8> %ld1, ptr %stptr1, align 1
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store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1
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ret void
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}
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define void @nxv16i8_outside_range(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv16i8_outside_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0, #-65, mul vl]
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; CHECK-NEXT: ldr z1, [x0, #-64, mul vl]
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; CHECK-NEXT: str z0, [x1, #64, mul vl]
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; CHECK-NEXT: str z1, [x1, #65, mul vl]
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; CHECK-NEXT: ret
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;
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; CHECK-BE-LABEL: nxv16i8_outside_range:
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; CHECK-BE: // %bb.0:
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; CHECK-BE-NEXT: rdvl x8, #1
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; CHECK-BE-NEXT: mov x9, #-1040 // =0xfffffffffffffbf0
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; CHECK-BE-NEXT: mov x10, #-1024 // =0xfffffffffffffc00
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; CHECK-BE-NEXT: lsr x8, x8, #4
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; CHECK-BE-NEXT: mov w11, #1024 // =0x400
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; CHECK-BE-NEXT: mov w12, #1040 // =0x410
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; CHECK-BE-NEXT: ptrue p0.b
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; CHECK-BE-NEXT: mul x9, x8, x9
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; CHECK-BE-NEXT: mul x10, x8, x10
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; CHECK-BE-NEXT: mul x11, x8, x11
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; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0, x9]
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; CHECK-BE-NEXT: mul x8, x8, x12
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; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, x10]
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; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1, x11]
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; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, x8]
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; CHECK-BE-NEXT: ret
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;
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; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8_outside_range:
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; CHECK-LDPALIGNEDONLY: // %bb.0:
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0, #-65, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #-64, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: str z0, [x1, #64, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: str z1, [x1, #65, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: ret
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;
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; CHECK-STPALIGNEDONLY-LABEL: nxv16i8_outside_range:
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; CHECK-STPALIGNEDONLY: // %bb.0:
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; CHECK-STPALIGNEDONLY-NEXT: ldr z0, [x0, #-65, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: ldr z1, [x0, #-64, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1, #64, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #65, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: ret
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;
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; CHECK-OFF-LABEL: nxv16i8_outside_range:
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; CHECK-OFF: // %bb.0:
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; CHECK-OFF-NEXT: ldr z0, [x0, #-65, mul vl]
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; CHECK-OFF-NEXT: ldr z1, [x0, #-64, mul vl]
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; CHECK-OFF-NEXT: str z0, [x1, #64, mul vl]
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; CHECK-OFF-NEXT: str z1, [x1, #65, mul vl]
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; CHECK-OFF-NEXT: ret
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%vscale = tail call i64 @llvm.vscale()
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%ldoff1 = mul i64 %vscale, -1040
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%ldoff2 = mul i64 %vscale, -1024
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%stoff1 = mul i64 %vscale, 1024
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%stoff2 = mul i64 %vscale, 1040
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%ldptr1 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff1
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%ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %ldoff2
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%stptr1 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff1
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%stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %stoff2
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%ld1 = load <vscale x 16 x i8>, ptr %ldptr1, align 1
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%ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1
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store <vscale x 16 x i8> %ld1, ptr %stptr1, align 1
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store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1
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ret void
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}
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define void @nxv16i8_2vl_stride(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv16i8_2vl_stride:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ldr z1, [x0, #2, mul vl]
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; CHECK-NEXT: str z0, [x1]
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; CHECK-NEXT: str z1, [x1, #2, mul vl]
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; CHECK-NEXT: ret
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;
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; CHECK-BE-LABEL: nxv16i8_2vl_stride:
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; CHECK-BE: // %bb.0:
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; CHECK-BE-NEXT: ptrue p0.b
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; CHECK-BE-NEXT: ld1b { z0.b }, p0/z, [x0]
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; CHECK-BE-NEXT: ld1b { z1.b }, p0/z, [x0, #2, mul vl]
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; CHECK-BE-NEXT: st1b { z0.b }, p0, [x1]
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; CHECK-BE-NEXT: st1b { z1.b }, p0, [x1, #2, mul vl]
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; CHECK-BE-NEXT: ret
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;
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; CHECK-LDPALIGNEDONLY-LABEL: nxv16i8_2vl_stride:
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; CHECK-LDPALIGNEDONLY: // %bb.0:
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z0, [x0]
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; CHECK-LDPALIGNEDONLY-NEXT: ldr z1, [x0, #2, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: str z0, [x1]
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; CHECK-LDPALIGNEDONLY-NEXT: str z1, [x1, #2, mul vl]
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; CHECK-LDPALIGNEDONLY-NEXT: ret
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;
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; CHECK-STPALIGNEDONLY-LABEL: nxv16i8_2vl_stride:
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; CHECK-STPALIGNEDONLY: // %bb.0:
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; CHECK-STPALIGNEDONLY-NEXT: ldr z0, [x0]
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; CHECK-STPALIGNEDONLY-NEXT: ldr z1, [x0, #2, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: str z0, [x1]
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; CHECK-STPALIGNEDONLY-NEXT: str z1, [x1, #2, mul vl]
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; CHECK-STPALIGNEDONLY-NEXT: ret
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;
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; CHECK-OFF-LABEL: nxv16i8_2vl_stride:
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; CHECK-OFF: // %bb.0:
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; CHECK-OFF-NEXT: ldr z0, [x0]
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; CHECK-OFF-NEXT: ldr z1, [x0, #2, mul vl]
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; CHECK-OFF-NEXT: str z0, [x1]
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; CHECK-OFF-NEXT: str z1, [x1, #2, mul vl]
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; CHECK-OFF-NEXT: ret
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%vscale = tail call i64 @llvm.vscale()
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%vl = shl nuw nsw i64 %vscale, 5
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%ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %vl
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%stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %vl
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%ld1 = load <vscale x 16 x i8>, ptr %ldptr, align 1
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%ld2 = load <vscale x 16 x i8>, ptr %ldptr2, align 1
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store <vscale x 16 x i8> %ld1, ptr %stptr, align 1
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store <vscale x 16 x i8> %ld2, ptr %stptr2, align 1
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ret void
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}
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define void @nxv2f64_32b_aligned(ptr %ldptr, ptr %stptr) {
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; CHECK-LABEL: nxv2f64_32b_aligned:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q0, q1, [x0]
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; CHECK-NEXT: stp q0, q1, [x1]
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; CHECK-NEXT: ret
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;
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; CHECK-BE-LABEL: nxv2f64_32b_aligned:
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; CHECK-BE: // %bb.0:
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; CHECK-BE-NEXT: ptrue p0.d
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; CHECK-BE-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-BE-NEXT: ld1d { z1.d }, p0/z, [x0, #1, mul vl]
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; CHECK-BE-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-BE-NEXT: st1d { z1.d }, p0, [x1, #1, mul vl]
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; CHECK-BE-NEXT: ret
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;
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; CHECK-LDPALIGNEDONLY-LABEL: nxv2f64_32b_aligned:
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; CHECK-LDPALIGNEDONLY: // %bb.0:
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; CHECK-LDPALIGNEDONLY-NEXT: ldp q0, q1, [x0]
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; CHECK-LDPALIGNEDONLY-NEXT: stp q0, q1, [x1]
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; CHECK-LDPALIGNEDONLY-NEXT: ret
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;
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; CHECK-STPALIGNEDONLY-LABEL: nxv2f64_32b_aligned:
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; CHECK-STPALIGNEDONLY: // %bb.0:
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; CHECK-STPALIGNEDONLY-NEXT: ldp q0, q1, [x0]
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; CHECK-STPALIGNEDONLY-NEXT: stp q0, q1, [x1]
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; CHECK-STPALIGNEDONLY-NEXT: ret
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;
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; CHECK-OFF-LABEL: nxv2f64_32b_aligned:
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; CHECK-OFF: // %bb.0:
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; CHECK-OFF-NEXT: ldr z0, [x0]
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; CHECK-OFF-NEXT: ldr z1, [x0, #1, mul vl]
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; CHECK-OFF-NEXT: str z0, [x1]
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; CHECK-OFF-NEXT: str z1, [x1, #1, mul vl]
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; CHECK-OFF-NEXT: ret
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%vscale = tail call i64 @llvm.vscale()
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%vl = shl nuw nsw i64 %vscale, 4
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%ldptr2 = getelementptr inbounds nuw i8, ptr %ldptr, i64 %vl
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%stptr2 = getelementptr inbounds nuw i8, ptr %stptr, i64 %vl
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%ld1 = load <vscale x 2 x double>, ptr %ldptr, align 32
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%ld2 = load <vscale x 2 x double>, ptr %ldptr2, align 32
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store <vscale x 2 x double> %ld1, ptr %stptr, align 32
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store <vscale x 2 x double> %ld2, ptr %stptr2, align 32
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ret void
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}
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