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Uniformity analysis is a generalization of divergence analysis to
include irreducible control flow:
1. The proposed spec presents a notion of "maximal convergence" that
captures the existing convention of converging threads at the
headers of natual loops.
2. Maximal convergence is then extended to irreducible cycles. The
identity of irreducible cycles is determined by the choices made
in a depth-first traversal of the control flow graph. Uniformity
analysis uses criteria that depend only on closed paths and not
cycles, to determine maximal convergence. This makes it a
conservative analysis that is independent of the effect of DFS on
CycleInfo.
3. The analysis is implemented as a template that can be
instantiated for both LLVM IR and Machine IR.
Validation:
- passes existing tests for divergence analysis
- passes new tests with irreducible control flow
- passes equivalent tests in MIR and GMIR
Based on concepts originally outlined by
Nicolai Haehnle <nicolai.haehnle@amd.com>
With contributions from Ruiling Song <ruiling.song@amd.com> and
Jay Foad <jay.foad@amd.com>.
Support for GMIR and lit tests for GMIR/MIR added by
Yashwant Singh <yashwant.singh@amd.com>.
Differential Revision: https://reviews.llvm.org/D130746
87 lines
2.6 KiB
C++
87 lines
2.6 KiB
C++
//===- MachineSSAContext.cpp ------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file defines a specialization of the GenericSSAContext<X>
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/// template class for Machine IR.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineSSAContext.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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const Register MachineSSAContext::ValueRefNull{};
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void MachineSSAContext::setFunction(MachineFunction &Fn) {
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MF = &Fn;
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RegInfo = &MF->getRegInfo();
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}
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MachineBasicBlock *MachineSSAContext::getEntryBlock(MachineFunction &F) {
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return &F.front();
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}
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void MachineSSAContext::appendBlockTerms(
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SmallVectorImpl<const MachineInstr *> &terms,
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const MachineBasicBlock &block) {
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for (auto &T : block.terminators())
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terms.push_back(&T);
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}
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void MachineSSAContext::appendBlockDefs(SmallVectorImpl<Register> &defs,
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const MachineBasicBlock &block) {
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for (const MachineInstr &instr : block.instrs()) {
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for (const MachineOperand &op : instr.operands()) {
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if (op.isReg() && op.isDef())
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defs.push_back(op.getReg());
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}
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}
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}
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/// Get the defining block of a value.
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MachineBasicBlock *MachineSSAContext::getDefBlock(Register value) const {
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if (!value)
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return nullptr;
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return RegInfo->getVRegDef(value)->getParent();
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}
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bool MachineSSAContext::isConstantValuePhi(const MachineInstr &Phi) {
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return Phi.isConstantValuePHI();
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}
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Printable MachineSSAContext::print(const MachineBasicBlock *Block) const {
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if (!Block)
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return Printable([](raw_ostream &Out) { Out << "<nullptr>"; });
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return Printable([Block](raw_ostream &Out) { Block->printName(Out); });
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}
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Printable MachineSSAContext::print(const MachineInstr *I) const {
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return Printable([I](raw_ostream &Out) { I->print(Out); });
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}
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Printable MachineSSAContext::print(Register Value) const {
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auto *MRI = RegInfo;
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return Printable([MRI, Value](raw_ostream &Out) {
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Out << printReg(Value, MRI->getTargetRegisterInfo(), 0, MRI);
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if (Value) {
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// Try to print the definition.
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if (auto *Instr = MRI->getUniqueVRegDef(Value)) {
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Out << ": ";
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Instr->print(Out);
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}
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}
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});
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}
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