mirror of
https://github.com/llvm/llvm-project.git
synced 2025-04-25 17:16:04 +00:00
37e6f84026
Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900). - Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements.
22 lines
610 B
ReStructuredText
22 lines
610 B
ReStructuredText
..
|
|
**************************************************
|
|
* *
|
|
* Automatically generated file, do not edit! *
|
|
* *
|
|
**************************************************
|
|
|
|
.. _amdgpu_synid_gfx10_sdata_c1aec6:
|
|
|
|
sdata
|
|
=====
|
|
|
|
Input data for an atomic instruction.
|
|
|
|
Optionally, this operand may be used to store output data:
|
|
|
|
* If :ref:`glc<amdgpu_synid_glc>` is specified, gets the memory value before the operation.
|
|
|
|
*Size:* 4 dwords.
|
|
|
|
*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`ttmp<amdgpu_synid_ttmp>`
|