llvm-project/llvm/docs/AMDGPU/gfx7_imm16_0533c2.rst
Dmitry Preobrazhensky cc426402be [AMDGPU][GFX7][DOC][NFC] Update assembler syntax description
Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205).
- Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783).
- Enable abs and neg modifiers for v_cndmask_b32_e64.
- Minor corrections and improvements.
2022-12-13 13:50:40 +03:00

14 lines
504 B
ReStructuredText

..
**************************************************
* *
* Automatically generated file, do not edit! *
* *
**************************************************
.. _amdgpu_synid_gfx7_imm16_0533c2:
imm16
=====
An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from -32768 to 65535.