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cc426402be
Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable abs and neg modifiers for v_cndmask_b32_e64. - Minor corrections and improvements.
37 lines
1.1 KiB
ReStructuredText
37 lines
1.1 KiB
ReStructuredText
..
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**************************************************
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* *
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* Automatically generated file, do not edit! *
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* *
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**************************************************
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.. _amdgpu_synid_gfx7_label:
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label
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=====
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A branch target, which is a 16-bit signed integer treated as a PC-relative dword offset.
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This operand may be specified as one of the following:
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* An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range from -32768 to 65535.
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* A :ref:`symbol<amdgpu_synid_symbol>` (for example, a label) representing a relocatable address in the same compilation unit where it is referred from. The value is handled as a 16-bit PC-relative dword offset to be resolved by a linker.
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Examples:
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.. parsed-literal::
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offset = 30
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label_1:
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label_2 = . + 4
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s_branch 32
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s_branch offset + 2
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s_branch label_1
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s_branch label_2
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s_branch label_3
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s_branch label_4
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label_3 = label_2 + 4
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label_4:
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