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cc426402be
Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable abs and neg modifiers for v_cndmask_b32_e64. - Minor corrections and improvements.
22 lines
998 B
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22 lines
998 B
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* Automatically generated file, do not edit! *
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**************************************************
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.. _amdgpu_synid_gfx7_soffset_67d76d:
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soffset
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=======
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An unsigned offset, which is added to the base address to get the memory address.
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* If offset is specified as a register, it supplies an unsigned byte offset but 2 lsb's are ignored.
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* If offset is specified as an :ref:`uimm32<amdgpu_synid_uimm32>`, it supplies a 32-bit unsigned byte offset but 2 lsb's are ignored.
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* If offset is specified as an :ref:`uimm8<amdgpu_synid_uimm8>`, it supplies an 8-bit unsigned dword offset.
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*Size:* 1 dword.
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*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`uimm8<amdgpu_synid_uimm8>`, :ref:`uimm32<amdgpu_synid_uimm32>`
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