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427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
100 lines
3.7 KiB
LLVM
100 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-BE
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; This test checks that LSR properly recognizes lxvp/stxvp as load/store
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; intrinsics to avoid generating x-form instructions instead of d-forms.
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declare <256 x i1> @llvm.ppc.vsx.lxvp(ptr)
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declare void @llvm.ppc.vsx.stxvp(<256 x i1>, ptr)
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define void @foo(i32 zeroext %n, ptr %ptr, ptr %ptr2) {
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; CHECK-LABEL: foo:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: cmplwi r3, 0
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; CHECK-NEXT: beqlr cr0
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; CHECK-NEXT: # %bb.1: # %for.body.lr.ph
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; CHECK-NEXT: addi r4, r4, 64
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; CHECK-NEXT: addi r5, r5, 64
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; CHECK-NEXT: mtctr r3
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_2: # %for.body
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; CHECK-NEXT: #
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; CHECK-NEXT: lxvp vsp34, -64(r4)
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; CHECK-NEXT: lxvp vsp36, -32(r4)
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; CHECK-NEXT: lxvp vsp32, 0(r4)
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; CHECK-NEXT: lxvp vsp38, 32(r4)
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; CHECK-NEXT: addi r4, r4, 1
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; CHECK-NEXT: stxvp vsp34, -64(r5)
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; CHECK-NEXT: stxvp vsp36, -32(r5)
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; CHECK-NEXT: stxvp vsp32, 0(r5)
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; CHECK-NEXT: stxvp vsp38, 32(r5)
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; CHECK-NEXT: addi r5, r5, 1
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; CHECK-NEXT: bdnz .LBB0_2
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; CHECK-NEXT: # %bb.3: # %for.cond.cleanup
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: foo:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: cmplwi r3, 0
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; CHECK-BE-NEXT: beqlr cr0
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; CHECK-BE-NEXT: # %bb.1: # %for.body.lr.ph
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; CHECK-BE-NEXT: addi r4, r4, 64
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; CHECK-BE-NEXT: addi r5, r5, 64
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; CHECK-BE-NEXT: mtctr r3
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; CHECK-BE-NEXT: .p2align 4
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; CHECK-BE-NEXT: .LBB0_2: # %for.body
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; CHECK-BE-NEXT: #
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; CHECK-BE-NEXT: lxvp vsp34, -64(r4)
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; CHECK-BE-NEXT: lxvp vsp36, -32(r4)
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; CHECK-BE-NEXT: lxvp vsp32, 0(r4)
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; CHECK-BE-NEXT: lxvp vsp38, 32(r4)
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; CHECK-BE-NEXT: addi r4, r4, 1
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; CHECK-BE-NEXT: stxvp vsp34, -64(r5)
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; CHECK-BE-NEXT: stxvp vsp36, -32(r5)
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; CHECK-BE-NEXT: stxvp vsp32, 0(r5)
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; CHECK-BE-NEXT: stxvp vsp38, 32(r5)
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; CHECK-BE-NEXT: addi r5, r5, 1
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; CHECK-BE-NEXT: bdnz .LBB0_2
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; CHECK-BE-NEXT: # %bb.3: # %for.cond.cleanup
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; CHECK-BE-NEXT: blr
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entry:
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%cmp35.not = icmp eq i32 %n, 0
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br i1 %cmp35.not, label %for.cond.cleanup, label %for.body.lr.ph
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for.body.lr.ph:
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%wide.trip.count = zext i32 %n to i64
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br label %for.body
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for.cond.cleanup:
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ret void
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for.body:
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%indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ]
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%0 = getelementptr i8, ptr %ptr, i64 %indvars.iv
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%1 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %0)
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%add2 = add nuw nsw i64 %indvars.iv, 32
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%2 = getelementptr i8, ptr %ptr, i64 %add2
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%3 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %2)
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%add4 = add nuw nsw i64 %indvars.iv, 64
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%4 = getelementptr i8, ptr %ptr, i64 %add4
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%5 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %4)
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%add6 = add nuw nsw i64 %indvars.iv, 96
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%6 = getelementptr i8, ptr %ptr, i64 %add6
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%7 = tail call <256 x i1> @llvm.ppc.vsx.lxvp(ptr %6)
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%8 = getelementptr i8, ptr %ptr2, i64 %indvars.iv
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tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %1, ptr %8)
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%9 = getelementptr i8, ptr %ptr2, i64 %add2
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tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %3, ptr %9)
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%10 = getelementptr i8, ptr %ptr2, i64 %add4
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tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %5, ptr %10)
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%11 = getelementptr i8, ptr %ptr2, i64 %add6
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tail call void @llvm.ppc.vsx.stxvp(<256 x i1> %7, ptr %11)
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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