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d0f9553ef5
This patch basically enables fast-isel for AIX 64-bit subtarget (previously enabled only for ELF 64). The initial motivation is to introduce branch folding to AIX generated code for correct debug behavior. I also saw some compiling time improvement in a few LLVM test-suite benchmarks. (toast, dbms, cjpeg, burg, etc.) Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D98844
52 lines
1.0 KiB
LLVM
52 lines
1.0 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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define i32 @shl() nounwind {
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entry:
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; PPC64: shl
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; PPC64: slw
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%shl = shl i32 -1, 2
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ret i32 %shl
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}
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define i32 @shl_reg(i32 %src1, i32 %src2) nounwind {
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entry:
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; PPC64: shl_reg
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; PPC64: slw
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%shl = shl i32 %src1, %src2
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ret i32 %shl
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}
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define i32 @lshr() nounwind {
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entry:
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; PPC64: lshr
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; PPC64: srw
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%lshr = lshr i32 -1, 2
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ret i32 %lshr
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}
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define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind {
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entry:
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; PPC64: lshr_reg
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; PPC64: srw
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%lshr = lshr i32 %src1, %src2
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ret i32 %lshr
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}
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define i32 @ashr() nounwind {
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entry:
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; PPC64: ashr
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; PPC64: srawi
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%ashr = ashr i32 -1, 2
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ret i32 %ashr
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}
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define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind {
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entry:
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; PPC64: ashr_reg
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; PPC64: sraw
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%ashr = ashr i32 %src1, %src2
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ret i32 %ashr
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}
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