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9df924a634
A new register class as well as a number of related subregisters are being added to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits long. These regsiters can also be used in consecutive pairs which leads to a register that is 2048 bits. This patch also adds 7 new instructions that use these registers. More instructions will be added in future patches. Reviewed By: amyk, saghir Differential Revision: https://reviews.llvm.org/D136366
30 lines
1.3 KiB
LLVM
30 lines
1.3 KiB
LLVM
; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs \
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; RUN: -mattr=paired-vector-memops,mma,rop-protect,privileged \
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; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
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; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs \
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; RUN: -mattr=paired-vector-memops,mma,rop-protect,privileged \
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; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
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; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs \
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; RUN: -mattr=paired-vector-memops,mma,rop-protect,privileged \
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; RUN: -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
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; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs \
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; RUN: -mattr=paired-vector-memops,mma,rop-protect,privileged \
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; RUN: -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \
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; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
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define dso_local signext i32 @f() {
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entry:
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ret i32 0
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}
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; Make sure that all of the features listed are recognized.
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; CHECK-NOT: is not a recognized feature for this target
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; Make sure that the test was actually compiled.
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; CHECK: li r3, 0
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; CHECK-NEXT: blr
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