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eece6ba283
AMDGPU has native instructions and target intrinsics for this, but these really should be subject to legalization and generic optimizations. This will enable legalization of f16->f32 on targets without f16 support. Implement a somewhat horrible inline expansion for targets without libcall support. This could be better if we could introduce control flow (GlobalISel version not yet implemented). Support for strictfp legalization is less complete but works for the simple cases.
67 lines
2.0 KiB
LLVM
67 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
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define float @call_ldexpf(float %a, i32 %b) {
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; CHECK-LABEL: call_ldexpf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: clrldi r4, r4, 32
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; CHECK-NEXT: bl ldexpf
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call float @ldexpf(float %a, i32 %b)
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ret float %result
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}
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define double @call_ldexp(double %a, i32 %b) {
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; CHECK-LABEL: call_ldexp:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: clrldi r4, r4, 32
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; CHECK-NEXT: bl ldexp
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call double @ldexp(double %a, i32 %b)
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ret double %result
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}
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define ppc_fp128 @call_ldexpl(ppc_fp128 %a, i32 %b) {
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; CHECK-LABEL: call_ldexpl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: clrldi r5, r5, 32
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; CHECK-NEXT: bl ldexpl
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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%result = call ppc_fp128 @ldexpl(ppc_fp128 %a, i32 %b)
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ret ppc_fp128 %result
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}
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declare float @ldexpf(float %a, i32 %b) #0
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declare double @ldexp(double %a, i32 %b) #0
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declare ppc_fp128 @ldexpl(ppc_fp128 %a, i32 %b) #0
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attributes #0 = { nounwind readonly }
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