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427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
208 lines
9.2 KiB
LLVM
208 lines
9.2 KiB
LLVM
; Test the loop alignment.
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; RUN: llc -verify-machineinstrs -mcpu=a2 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,GENERIC
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR
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; Test the loop alignment and the option -disable-ppc-innermost-loop-align32.
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; RUN: llc -verify-machineinstrs -mcpu=a2 -disable-ppc-innermost-loop-align32 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,GENERIC-DISABLE-PPC-INNERMOST-LOOP-ALIGN32
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -disable-ppc-innermost-loop-align32 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -disable-ppc-innermost-loop-align32 -mtriple powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -disable-ppc-innermost-loop-align32 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -disable-ppc-innermost-loop-align32 -mtriple powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefixes=CHECK,PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32
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%struct.parm = type { ptr, i32, i32 }
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; Test the loop alignment when the innermost hot loop has more than 8 instructions.
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define void @big_loop(ptr %arg) {
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entry:
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%localArg.sroa.0.0.copyload = load ptr, ptr %arg, align 8
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%localArg.sroa.4.0..sroa_idx56 = getelementptr inbounds %struct.parm, ptr %arg, i64 0, i32 1
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%localArg.sroa.4.0.copyload = load i32, ptr %localArg.sroa.4.0..sroa_idx56, align 8
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%localArg.sroa.5.0..sroa_idx58 = getelementptr inbounds %struct.parm, ptr %arg, i64 0, i32 2
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%localArg.sroa.5.0.copyload = load i32, ptr %localArg.sroa.5.0..sroa_idx58, align 4
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%0 = sext i32 %localArg.sroa.5.0.copyload to i64
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br label %do.body
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do.body: ; preds = %do.end, %entry
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%m.0 = phi i32 [ %localArg.sroa.4.0.copyload, %entry ], [ %dec24, %do.end ]
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br label %do.body3
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do.body3: ; preds = %do.body3, %do.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %do.body3 ], [ %0, %do.body ]
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%1 = add nsw i64 %indvars.iv, 2
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%arrayidx = getelementptr inbounds i32, ptr %localArg.sroa.0.0.copyload, i64 %1
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%2 = add nsw i64 %indvars.iv, 3
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%3 = trunc i64 %1 to i32
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%4 = add nsw i64 %indvars.iv, 4
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%arrayidx10 = getelementptr inbounds i32, ptr %localArg.sroa.0.0.copyload, i64 %2
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%5 = trunc i64 %2 to i32
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store i32 %5, ptr %arrayidx10, align 4
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%arrayidx12 = getelementptr inbounds i32, ptr %localArg.sroa.0.0.copyload, i64 %4
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%6 = trunc i64 %4 to i32
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store i32 %6, ptr %arrayidx12, align 4
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store i32 %3, ptr %arrayidx, align 4
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%arrayidx21 = getelementptr inbounds i32, ptr %localArg.sroa.0.0.copyload, i64 %indvars.iv
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%7 = trunc i64 %indvars.iv to i32
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%8 = add i32 %7, 1
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store i32 %8, ptr %arrayidx21, align 4
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%indvars.iv.next = add nsw i64 %indvars.iv, -1
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%9 = icmp eq i64 %indvars.iv, 0
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br i1 %9, label %do.end, label %do.body3
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do.end: ; preds = %do.body3
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%dec24 = add nsw i32 %m.0, -1
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%tobool25 = icmp eq i32 %m.0, 0
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br i1 %tobool25, label %do.end26, label %do.body
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do.end26: ; preds = %do.end
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%arrayidx28 = getelementptr inbounds i32, ptr %localArg.sroa.0.0.copyload, i64 %0
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store i32 0, ptr %arrayidx28, align 4
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ret void
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; CHECK-LABEL: @big_loop
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; CHECK: mtctr
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; GENERIC: .p2align 4
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; PWR: .p2align 5
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; GENERIC-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
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; PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
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; CHECK: bdnz
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}
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; Test the loop alignment when the innermost hot loop has 5-8 instructions.
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define void @general_loop(ptr %s, i64 %m) {
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entry:
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%tobool40 = icmp eq i64 %m, 0
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br i1 %tobool40, label %while.end18, label %while.body3.lr.ph
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while.cond.loopexit: ; preds = %while.body3
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%tobool = icmp eq i64 %dec, 0
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br i1 %tobool, label %while.end18, label %while.body3.lr.ph
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while.body3.lr.ph: ; preds = %entry, %while.cond.loopexit
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%m.addr.041 = phi i64 [ %dec, %while.cond.loopexit ], [ %m, %entry ]
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%dec = add nsw i64 %m.addr.041, -1
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%conv = trunc i64 %m.addr.041 to i32
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%conv11 = trunc i64 %dec to i32
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br label %while.body3
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while.body3: ; preds = %while.body3.lr.ph, %while.body3
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%n.039 = phi i64 [ %m.addr.041, %while.body3.lr.ph ], [ %dec16, %while.body3 ]
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%inc = add nsw i64 %n.039, 1
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%arrayidx = getelementptr inbounds i32, ptr %s, i64 %n.039
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%inc5 = add nsw i64 %n.039, 2
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%arrayidx6 = getelementptr inbounds i32, ptr %s, i64 %inc
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%sub = sub nsw i64 %dec, %inc5
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%conv7 = trunc i64 %sub to i32
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%arrayidx9 = getelementptr inbounds i32, ptr %s, i64 %inc5
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store i32 %conv7, ptr %arrayidx9, align 4
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store i32 %conv11, ptr %arrayidx6, align 4
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store i32 %conv, ptr %arrayidx, align 4
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%dec16 = add nsw i64 %n.039, -1
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%tobool2 = icmp eq i64 %dec16, 0
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br i1 %tobool2, label %while.cond.loopexit, label %while.body3
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while.end18: ; preds = %while.cond.loopexit, %entry
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ret void
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; CHECK-LABEL: @general_loop
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; CHECK: mtctr
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; GENERIC: .p2align 4
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; PWR: .p2align 5
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; GENERIC-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
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; PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 5
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; CHECK: bdnz
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}
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; Test the small loop alignment when the innermost hot loop has less than 4 instructions.
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define void @small_loop(i64 %m) {
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entry:
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br label %do.body
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do.body: ; preds = %do.end, %entry
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%m.addr.0 = phi i64 [ %m, %entry ], [ %1, %do.end ]
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br label %do.body1
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do.body1: ; preds = %do.body1, %do.body
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%n.0 = phi i64 [ %m.addr.0, %do.body ], [ %0, %do.body1 ]
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%0 = tail call i64 asm "subi $0,$0,1", "=r,0"(i64 %n.0)
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%tobool = icmp eq i64 %0, 0
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br i1 %tobool, label %do.end, label %do.body1
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do.end: ; preds = %do.body1
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%1 = tail call i64 asm "subi $1,$1,1", "=r,0"(i64 %m.addr.0)
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%tobool3 = icmp eq i64 %1, 0
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br i1 %tobool3, label %do.end4, label %do.body
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do.end4: ; preds = %do.end
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ret void
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; CHECK-LABEL: @small_loop
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; CHECK: mr
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; GENERIC: .p2align 4
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; PWR: .p2align 5
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; GENERIC-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
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; PWR-DISABLE-PPC-INNERMOST-LOOP-ALIGN32: .p2align 4
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; CHECK: bne
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}
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; Test the loop alignment when the innermost cold loop has more than 8 instructions.
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define void @big_loop_cold_innerloop(ptr %arg) {
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entry:
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%localArg.sroa.0.0.copyload = load ptr, ptr %arg, align 8
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%localArg.sroa.4.0..sroa_idx56 = getelementptr inbounds %struct.parm, ptr %arg, i64 0, i32 1
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%localArg.sroa.4.0.copyload = load i32, ptr %localArg.sroa.4.0..sroa_idx56, align 8
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%localArg.sroa.5.0..sroa_idx58 = getelementptr inbounds %struct.parm, ptr %arg, i64 0, i32 2
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%localArg.sroa.5.0.copyload = load i32, ptr %localArg.sroa.5.0..sroa_idx58, align 4
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%0 = sext i32 %localArg.sroa.5.0.copyload to i64
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br label %do.body
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do.body: ; preds = %do.end, %entry
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%m.0 = phi i32 [ %localArg.sroa.4.0.copyload, %entry ], [ %dec24, %do.end ]
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br label %do.body3
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do.body3: ; preds = %do.body3, %do.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %do.body3 ], [ %0, %do.body ]
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%1 = add nsw i64 %indvars.iv, 2
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%arrayidx = getelementptr inbounds i32, ptr %localArg.sroa.0.0.copyload, i64 %1
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%2 = add nsw i64 %indvars.iv, 3
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%3 = trunc i64 %1 to i32
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%4 = add nsw i64 %indvars.iv, 4
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%arrayidx10 = getelementptr inbounds i32, ptr %localArg.sroa.0.0.copyload, i64 %2
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%5 = trunc i64 %2 to i32
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store i32 %5, ptr %arrayidx10, align 4
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%arrayidx12 = getelementptr inbounds i32, ptr %localArg.sroa.0.0.copyload, i64 %4
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%6 = trunc i64 %4 to i32
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store i32 %6, ptr %arrayidx12, align 4
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store i32 %3, ptr %arrayidx, align 4
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%arrayidx21 = getelementptr inbounds i32, ptr %localArg.sroa.0.0.copyload, i64 %indvars.iv
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%7 = trunc i64 %indvars.iv to i32
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%8 = add i32 %7, 1
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store i32 %8, ptr %arrayidx21, align 4
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%indvars.iv.next = add nsw i64 %indvars.iv, -1
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%9 = icmp eq i64 %indvars.iv, 0
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br i1 %9, label %do.end, label %do.body3
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do.end: ; preds = %do.body3
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%dec24 = add nsw i32 %m.0, -1
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%tobool25 = icmp eq i32 %m.0, 0
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br i1 %tobool25, label %do.end26, label %do.body
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do.end26: ; preds = %do.end
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%arrayidx28 = getelementptr inbounds i32, ptr %localArg.sroa.0.0.copyload, i64 %0
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store i32 0, ptr %arrayidx28, align 4
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ret void
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; CHECK-LABEL: @big_loop_cold_innerloop
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; CHECK: mtctr
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; PWR: .p2align 5
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; CHECK-NOT: .p2align 5
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; CHECK: bdnz
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}
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