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The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
44 lines
1.6 KiB
LLVM
44 lines
1.6 KiB
LLVM
; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr8 \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr9 \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s \
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; RUN: | FileCheck %s --check-prefix=CHECK-P9UP --implicit-check-not xxswapd
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; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr9 -mattr=-power9-vector \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr10 \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s \
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; RUN: | FileCheck %s --check-prefix=CHECK-P9UP
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; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr10 \
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; RUN: -mtriple=powerpc64-unknown-unknown < %s \
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; RUN: | FileCheck %s --check-prefix=CHECK-P9UP
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; Function Attrs: nounwind
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define void @test() {
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entry:
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%__a.addr.i = alloca i32, align 4
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%__b.addr.i = alloca ptr, align 8
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%i = alloca <4 x i32>, align 16
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%j = alloca <4 x i32>, align 16
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store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr %i, align 16
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store i32 0, ptr %__a.addr.i, align 4
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store ptr %i, ptr %__b.addr.i, align 8
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%0 = load i32, ptr %__a.addr.i, align 4
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%1 = load ptr, ptr %__b.addr.i, align 8
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%2 = getelementptr i8, ptr %1, i32 %0
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%3 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr %2)
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; CHECK: lwa [[REG0:[0-9]+]],
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; CHECK: lxvd2x [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]]
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; CHECK: xxswapd [[REG1]], [[REG1]]
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; CHECK-P9UP: lwa [[REG0:[0-9]+]],
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; CHECK-P9UP: lxvx [[REG1:[0-9]+]], {{[0-9]+}}, [[REG0]]
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store <4 x i32> %3, ptr %j, align 16
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ret void
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}
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; Function Attrs: nounwind readonly
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declare <4 x i32> @llvm.ppc.vsx.lxvw4x(ptr)
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