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e9d12c2480
This patch only adds tests for PowerPC. The purpose of these tests is to track what code is generated for various vector reductions. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D113801
205 lines
6.4 KiB
LLVM
205 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr9 -mtriple=powerpc64le < %s | FileCheck %s --check-prefix=PWR9LE
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr9 -mtriple=powerpc64 < %s | FileCheck %s --check-prefix=PWR9BE
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr10 -mtriple=powerpc64le < %s | FileCheck %s --check-prefix=PWR10LE
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; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mcpu=pwr10 -mtriple=powerpc64 < %s | FileCheck %s --check-prefix=PWR10BE
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define dso_local i32 @v2i32(<2 x i32> %a) local_unnamed_addr #0 {
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; PWR9LE-LABEL: v2i32:
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; PWR9LE: # %bb.0: # %entry
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; PWR9LE-NEXT: xxspltw v3, v2, 2
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; PWR9LE-NEXT: li r3, 0
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; PWR9LE-NEXT: vmuluwm v2, v2, v3
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; PWR9LE-NEXT: vextuwrx r3, r3, v2
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; PWR9LE-NEXT: blr
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;
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; PWR9BE-LABEL: v2i32:
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; PWR9BE: # %bb.0: # %entry
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; PWR9BE-NEXT: xxspltw v3, v2, 1
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; PWR9BE-NEXT: li r3, 0
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; PWR9BE-NEXT: vmuluwm v2, v2, v3
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; PWR9BE-NEXT: vextuwlx r3, r3, v2
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; PWR9BE-NEXT: blr
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;
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; PWR10LE-LABEL: v2i32:
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; PWR10LE: # %bb.0: # %entry
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; PWR10LE-NEXT: xxspltw v3, v2, 2
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; PWR10LE-NEXT: li r3, 0
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; PWR10LE-NEXT: vmuluwm v2, v2, v3
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; PWR10LE-NEXT: vextuwrx r3, r3, v2
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; PWR10LE-NEXT: blr
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;
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; PWR10BE-LABEL: v2i32:
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; PWR10BE: # %bb.0: # %entry
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; PWR10BE-NEXT: xxspltw v3, v2, 1
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; PWR10BE-NEXT: li r3, 0
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; PWR10BE-NEXT: vmuluwm v2, v2, v3
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; PWR10BE-NEXT: vextuwlx r3, r3, v2
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; PWR10BE-NEXT: blr
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entry:
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%0 = call i32 @llvm.vector.reduce.mul.v2i32(<2 x i32> %a)
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ret i32 %0
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}
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define dso_local i32 @v4i32(<4 x i32> %a) local_unnamed_addr #0 {
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; PWR9LE-LABEL: v4i32:
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; PWR9LE: # %bb.0: # %entry
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; PWR9LE-NEXT: xxswapd v3, v2
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; PWR9LE-NEXT: li r3, 0
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; PWR9LE-NEXT: vmuluwm v2, v2, v3
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; PWR9LE-NEXT: xxspltw v3, v2, 2
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; PWR9LE-NEXT: vmuluwm v2, v2, v3
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; PWR9LE-NEXT: vextuwrx r3, r3, v2
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; PWR9LE-NEXT: blr
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;
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; PWR9BE-LABEL: v4i32:
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; PWR9BE: # %bb.0: # %entry
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; PWR9BE-NEXT: xxswapd v3, v2
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; PWR9BE-NEXT: li r3, 0
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; PWR9BE-NEXT: vmuluwm v2, v2, v3
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; PWR9BE-NEXT: xxspltw v3, v2, 1
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; PWR9BE-NEXT: vmuluwm v2, v2, v3
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; PWR9BE-NEXT: vextuwlx r3, r3, v2
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; PWR9BE-NEXT: blr
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;
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; PWR10LE-LABEL: v4i32:
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; PWR10LE: # %bb.0: # %entry
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; PWR10LE-NEXT: xxswapd v3, v2
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; PWR10LE-NEXT: li r3, 0
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; PWR10LE-NEXT: vmuluwm v2, v2, v3
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; PWR10LE-NEXT: xxspltw v3, v2, 2
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; PWR10LE-NEXT: vmuluwm v2, v2, v3
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; PWR10LE-NEXT: vextuwrx r3, r3, v2
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; PWR10LE-NEXT: blr
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;
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; PWR10BE-LABEL: v4i32:
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; PWR10BE: # %bb.0: # %entry
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; PWR10BE-NEXT: xxswapd v3, v2
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; PWR10BE-NEXT: li r3, 0
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; PWR10BE-NEXT: vmuluwm v2, v2, v3
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; PWR10BE-NEXT: xxspltw v3, v2, 1
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; PWR10BE-NEXT: vmuluwm v2, v2, v3
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; PWR10BE-NEXT: vextuwlx r3, r3, v2
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; PWR10BE-NEXT: blr
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entry:
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%0 = call i32 @llvm.vector.reduce.mul.v4i32(<4 x i32> %a)
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ret i32 %0
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}
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define dso_local i32 @v8i32(<8 x i32> %a) local_unnamed_addr #0 {
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; PWR9LE-LABEL: v8i32:
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; PWR9LE: # %bb.0: # %entry
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; PWR9LE-NEXT: vmuluwm v2, v2, v3
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; PWR9LE-NEXT: li r3, 0
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; PWR9LE-NEXT: xxswapd v3, v2
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; PWR9LE-NEXT: vmuluwm v2, v2, v3
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; PWR9LE-NEXT: xxspltw v3, v2, 2
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; PWR9LE-NEXT: vmuluwm v2, v2, v3
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; PWR9LE-NEXT: vextuwrx r3, r3, v2
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; PWR9LE-NEXT: blr
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;
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; PWR9BE-LABEL: v8i32:
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; PWR9BE: # %bb.0: # %entry
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; PWR9BE-NEXT: vmuluwm v2, v2, v3
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; PWR9BE-NEXT: li r3, 0
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; PWR9BE-NEXT: xxswapd v3, v2
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; PWR9BE-NEXT: vmuluwm v2, v2, v3
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; PWR9BE-NEXT: xxspltw v3, v2, 1
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; PWR9BE-NEXT: vmuluwm v2, v2, v3
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; PWR9BE-NEXT: vextuwlx r3, r3, v2
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; PWR9BE-NEXT: blr
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;
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; PWR10LE-LABEL: v8i32:
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; PWR10LE: # %bb.0: # %entry
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; PWR10LE-NEXT: vmuluwm v2, v2, v3
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; PWR10LE-NEXT: li r3, 0
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; PWR10LE-NEXT: xxswapd v3, v2
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; PWR10LE-NEXT: vmuluwm v2, v2, v3
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; PWR10LE-NEXT: xxspltw v3, v2, 2
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; PWR10LE-NEXT: vmuluwm v2, v2, v3
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; PWR10LE-NEXT: vextuwrx r3, r3, v2
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; PWR10LE-NEXT: blr
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;
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; PWR10BE-LABEL: v8i32:
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; PWR10BE: # %bb.0: # %entry
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; PWR10BE-NEXT: vmuluwm v2, v2, v3
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; PWR10BE-NEXT: li r3, 0
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; PWR10BE-NEXT: xxswapd v3, v2
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; PWR10BE-NEXT: vmuluwm v2, v2, v3
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; PWR10BE-NEXT: xxspltw v3, v2, 1
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; PWR10BE-NEXT: vmuluwm v2, v2, v3
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; PWR10BE-NEXT: vextuwlx r3, r3, v2
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; PWR10BE-NEXT: blr
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entry:
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%0 = call i32 @llvm.vector.reduce.mul.v8i32(<8 x i32> %a)
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ret i32 %0
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}
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define dso_local i32 @v16i32(<16 x i32> %a) local_unnamed_addr #0 {
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; PWR9LE-LABEL: v16i32:
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; PWR9LE: # %bb.0: # %entry
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; PWR9LE-NEXT: vmuluwm v3, v3, v5
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; PWR9LE-NEXT: vmuluwm v2, v2, v4
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; PWR9LE-NEXT: li r3, 0
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; PWR9LE-NEXT: vmuluwm v2, v2, v3
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; PWR9LE-NEXT: xxswapd v3, v2
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; PWR9LE-NEXT: vmuluwm v2, v2, v3
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; PWR9LE-NEXT: xxspltw v3, v2, 2
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; PWR9LE-NEXT: vmuluwm v2, v2, v3
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; PWR9LE-NEXT: vextuwrx r3, r3, v2
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; PWR9LE-NEXT: blr
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;
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; PWR9BE-LABEL: v16i32:
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; PWR9BE: # %bb.0: # %entry
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; PWR9BE-NEXT: vmuluwm v3, v3, v5
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; PWR9BE-NEXT: vmuluwm v2, v2, v4
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; PWR9BE-NEXT: li r3, 0
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; PWR9BE-NEXT: vmuluwm v2, v2, v3
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; PWR9BE-NEXT: xxswapd v3, v2
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; PWR9BE-NEXT: vmuluwm v2, v2, v3
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; PWR9BE-NEXT: xxspltw v3, v2, 1
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; PWR9BE-NEXT: vmuluwm v2, v2, v3
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; PWR9BE-NEXT: vextuwlx r3, r3, v2
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; PWR9BE-NEXT: blr
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;
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; PWR10LE-LABEL: v16i32:
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; PWR10LE: # %bb.0: # %entry
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; PWR10LE-NEXT: vmuluwm v3, v3, v5
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; PWR10LE-NEXT: vmuluwm v2, v2, v4
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; PWR10LE-NEXT: li r3, 0
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; PWR10LE-NEXT: vmuluwm v2, v2, v3
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; PWR10LE-NEXT: xxswapd v3, v2
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; PWR10LE-NEXT: vmuluwm v2, v2, v3
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; PWR10LE-NEXT: xxspltw v3, v2, 2
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; PWR10LE-NEXT: vmuluwm v2, v2, v3
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; PWR10LE-NEXT: vextuwrx r3, r3, v2
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; PWR10LE-NEXT: blr
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;
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; PWR10BE-LABEL: v16i32:
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; PWR10BE: # %bb.0: # %entry
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; PWR10BE-NEXT: vmuluwm v3, v3, v5
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; PWR10BE-NEXT: vmuluwm v2, v2, v4
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; PWR10BE-NEXT: li r3, 0
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; PWR10BE-NEXT: vmuluwm v2, v2, v3
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; PWR10BE-NEXT: xxswapd v3, v2
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; PWR10BE-NEXT: vmuluwm v2, v2, v3
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; PWR10BE-NEXT: xxspltw v3, v2, 1
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; PWR10BE-NEXT: vmuluwm v2, v2, v3
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; PWR10BE-NEXT: vextuwlx r3, r3, v2
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; PWR10BE-NEXT: blr
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entry:
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%0 = call i32 @llvm.vector.reduce.mul.v16i32(<16 x i32> %a)
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ret i32 %0
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}
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declare i32 @llvm.vector.reduce.mul.v2i32(<2 x i32>) #0
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declare i32 @llvm.vector.reduce.mul.v4i32(<4 x i32>) #0
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declare i32 @llvm.vector.reduce.mul.v8i32(<8 x i32>) #0
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declare i32 @llvm.vector.reduce.mul.v16i32(<16 x i32>) #0
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attributes #0 = { nounwind }
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