Florian Hahn 437d587e48

[LV] Add outer loop test with different successor orders in inner latch.

2025-03-09 18:13:06 +00:00

..

Analysis

[AArch64] Improve vector funnel shift by constant costs. (#130044)

2025-03-09 18:01:45 +00:00

Assembler

[RISCV][VLS] Support RISCV VLS calling convention (#100346)

2025-03-03 12:39:35 +08:00

Bindings

…

Bitcode

[RISCV][VLS] Support RISCV VLS calling convention (#100346)

2025-03-03 12:39:35 +08:00

BugPoint

…

CodeGen

[X86] Combine bitcast(v1Ty insert_vector_elt(X, Y, 0)) to Y (#130475)

2025-03-09 20:10:08 +08:00

DebugInfo

Two fixes for DISubrangeType (#130345)

2025-03-07 14:23:05 -08:00

Demangle

…

Examples

…

ExecutionEngine

[JITLink][AArch64] Ensure that nulls remain null during ptrauth signing.

2025-02-28 15:19:41 +11:00

Feature

…

FileCheck

…

Frontend/HLSL

…

Instrumentation

[msan] Apply handleVectorReduceIntrinsic to max/min vector instructions (#129819)

2025-03-08 19:31:48 -08:00

Integer

…

JitListener

…

Linker

…

LTO

[LTO] Override TargetABI from module flags if present when creating TargetMachine (#126497)

2025-03-07 14:09:26 +08:00

MachineVerifier

AMDGPU: Add pseudoinstruction for agpr or vgpr constants (#130042)

2025-03-07 09:18:22 +07:00

MC

[AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. (#130302)

2025-03-08 01:10:09 +00:00

Object

…

ObjectYAML

…

Other

Optionally print !prof metadata inline (#130303)

2025-03-07 12:22:13 -08:00

SafepointIRVerifier

…

Support

…

SymbolRewriter

…

TableGen

…

ThinLTO

[ctxprof] Prepare profile format for flat profiles (#129626)

2025-03-05 07:22:35 -08:00

tools

[llvm-ar] Fix darwin-related tests' XFAIL annotation (#130144)

2025-03-07 10:53:10 +00:00

Transforms

[LV] Add outer loop test with different successor orders in inner latch.

2025-03-09 18:13:06 +00:00

Unit

…

Verifier

…

YAMLParser

…

.clang-format

…

CMakeLists.txt

…

lit.cfg.py

…

lit.site.cfg.py.in

…

TestRunner.sh

…