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llvm-project/llvm/test/MachineVerifier
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Michael Maitland 2f400a2fd7
[GISEL] Add G_VSCALE instruction (#84542)
2024-03-12 20:22:49 -04:00
..
convergencectrl/AMDGPU
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
copy-scalable.mir
[MachineVerifier] Fix COPY check in MachineVerifier for scalable vectors
2023-11-07 14:49:38 -08:00
generic-vreg-undef-use.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
live-ins-01.mir
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live-ins-02.mir
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live-ins-03.mir
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register-killed-inside-loop.mir
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test_copy_mismatch_types.mir
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test_copy_physregs_x86.mir
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test_copy.mir
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test_g_add.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_addrspacecast.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_assert_align.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_assert_sext_register_bank_class.mir
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test_g_assert_sext.mir
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test_g_assert_zext_register_bank_class.mir
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test_g_assert_zext.mir
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test_g_bitcast.mir
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test_g_brindirect_is_indirect_branch.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
test_g_brjt_is_indirect_branch.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
test_g_brjt.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_bswap.mir
[GISel] Restrict G_BSWAP to multiples of 16 bits. (#70245)
2023-10-30 10:27:57 -07:00
test_g_build_vector_trunc.mir
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test_g_build_vector.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_bzero.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_concat_vectors.mir
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test_g_constant_pool.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_constant.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_dyn_stackalloc.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_extract_subvector.mir
[GISEL] Add G_INSERT_SUBVECTOR and G_EXTRACT_SUBVECTOR (#84538)
2024-03-11 13:47:30 -04:00
test_g_extract.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_fcmp.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_fconstant.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_icmp.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_insert_subvector.mir
[GISEL] Add G_INSERT_SUBVECTOR and G_EXTRACT_SUBVECTOR (#84538)
2024-03-11 13:47:30 -04:00
test_g_insert.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_intrinsic_w_side_effects.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
test_g_intrinsic.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
test_g_inttoptr.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_invoke_region_start.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_is_fpclass.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_jump_table.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_llround.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_load.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_lround.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_memcpy_inline.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_memcpy.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_memmove.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_memset.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_merge_values.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_phi.mir
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test_g_prefetch.mir
[GlobalISel] Add G_PREFETCH (#74863)
2023-12-11 11:06:50 +00:00
test_g_ptr_add.mir
[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)
2024-03-09 09:07:22 +00:00
test_g_ptrmask.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_ptrtoint.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_rotr_rotl.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_select.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_sext_inreg.mir
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test_g_sextload.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_shift.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_shuffle_vector.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_splat_vector.mir
[GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378)
2024-03-07 09:10:03 -08:00
test_g_store.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_trunc.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_ubfx_sbfx.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_unmerge_values.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_g_vscale.mir
[GISEL] Add G_VSCALE instruction (#84542)
2024-03-12 20:22:49 -04:00
test_g_zextload.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_insert_subreg.mir
[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64
2023-09-29 10:13:06 -07:00
test_phis_precede_nonphis.mir
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test_vector_reductions.mir
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undef-should-only-be-set-on-subreg-defs.mir
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undef-virt-reg-entry-block.mir
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undef-virt-reg-nonentry-block.mir
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verifier-ec-subreg-liveness.mir
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verifier-generic-extend-truncate.mir
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verifier-generic-types-1.mir
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verifier-generic-types-2.mir
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verifier-implicit-virtreg-invalid-physreg-liveness.mir
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verifier-phi-fail0.mir
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verifier-phi.mir
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verifier-pseudo-terminators.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
verifier-statepoint.mir
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verify-implicit-def.mir
MachineVerifier: Reject extra non-register operands on instructions (#73758)
2023-11-30 22:33:42 +09:00
verify-inlineasmbr.mir
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verify-reg-sequence.mir
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verify-regbankselected-dbg-undef-use.mir
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verify-regbankselected.mir
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verify-regops.mir
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verify-selected-dbg-undef-use.mir
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verify-selected.mir
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writelane_m0.mir
[FIX] Require AMDGPU target in test case llvm/test/MachineVerifier/writelane_m0.mir
2024-01-30 15:47:19 -05:00