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2fc7a72733
This PR addresses a TODO in lib/Target/SPIRV/SPIRVInstructionSelector.cpp by adding implementation of the non-const G_BUILD_VECTOR, and fix emission of the OpGroupBroadcast instruction for the case when the `..._group_broadcast` builtin has more than one `local_id` argument and `OpGroupBroadcast` requires a newly constructed vector with 2 or 3 components instead of originally passed series of `local_id` arguments. This PR may resolve https://github.com/llvm/llvm-project/issues/97310 if the reason for the reported fail is an incorrectly generated OpGroupBroadcast instruction that was definitely a case. Existing test is hardened and a new test is added to cover this special case of the OpGroupBroadcast instruction emission.
919 lines
36 KiB
C++
919 lines
36 KiB
C++
//===-- SPIRVPreLegalizer.cpp - prepare IR for legalization -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The pass prepares IR for legalization: it assigns SPIR-V types to registers
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// and removes intrinsics which holded these types during IR translation.
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// Also it processes constants and registers them in GR to avoid duplication.
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//
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//===----------------------------------------------------------------------===//
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#include "SPIRV.h"
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#include "SPIRVSubtarget.h"
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#include "SPIRVUtils.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/Analysis/OptimizationRemarkEmitter.h"
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#include "llvm/IR/Attributes.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/DebugInfoMetadata.h"
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#include "llvm/IR/IntrinsicsSPIRV.h"
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#include "llvm/Target/TargetIntrinsicInfo.h"
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#define DEBUG_TYPE "spirv-prelegalizer"
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using namespace llvm;
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namespace {
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class SPIRVPreLegalizer : public MachineFunctionPass {
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public:
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static char ID;
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SPIRVPreLegalizer() : MachineFunctionPass(ID) {
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initializeSPIRVPreLegalizerPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // namespace
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static void
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addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR,
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const SPIRVSubtarget &STI,
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DenseMap<MachineInstr *, Type *> &TargetExtConstTypes,
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SmallSet<Register, 4> &TrackedConstRegs) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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DenseMap<MachineInstr *, Register> RegsAlreadyAddedToDT;
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SmallVector<MachineInstr *, 10> ToErase, ToEraseComposites;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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if (!isSpvIntrinsic(MI, Intrinsic::spv_track_constant))
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continue;
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ToErase.push_back(&MI);
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Register SrcReg = MI.getOperand(2).getReg();
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auto *Const =
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cast<Constant>(cast<ConstantAsMetadata>(
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MI.getOperand(3).getMetadata()->getOperand(0))
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->getValue());
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if (auto *GV = dyn_cast<GlobalValue>(Const)) {
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Register Reg = GR->find(GV, &MF);
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if (!Reg.isValid())
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GR->add(GV, &MF, SrcReg);
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else
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RegsAlreadyAddedToDT[&MI] = Reg;
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} else {
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Register Reg = GR->find(Const, &MF);
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if (!Reg.isValid()) {
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if (auto *ConstVec = dyn_cast<ConstantDataVector>(Const)) {
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auto *BuildVec = MRI.getVRegDef(SrcReg);
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assert(BuildVec &&
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BuildVec->getOpcode() == TargetOpcode::G_BUILD_VECTOR);
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for (unsigned i = 0; i < ConstVec->getNumElements(); ++i) {
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// Ensure that OpConstantComposite reuses a constant when it's
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// already created and available in the same machine function.
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Constant *ElemConst = ConstVec->getElementAsConstant(i);
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Register ElemReg = GR->find(ElemConst, &MF);
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if (!ElemReg.isValid())
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GR->add(ElemConst, &MF, BuildVec->getOperand(1 + i).getReg());
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else
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BuildVec->getOperand(1 + i).setReg(ElemReg);
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}
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}
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GR->add(Const, &MF, SrcReg);
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TrackedConstRegs.insert(SrcReg);
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if (Const->getType()->isTargetExtTy()) {
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// remember association so that we can restore it when assign types
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MachineInstr *SrcMI = MRI.getVRegDef(SrcReg);
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if (SrcMI && (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT ||
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SrcMI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF))
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TargetExtConstTypes[SrcMI] = Const->getType();
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if (Const->isNullValue()) {
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MachineIRBuilder MIB(MF);
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SPIRVType *ExtType =
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GR->getOrCreateSPIRVType(Const->getType(), MIB);
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SrcMI->setDesc(STI.getInstrInfo()->get(SPIRV::OpConstantNull));
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SrcMI->addOperand(MachineOperand::CreateReg(
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GR->getSPIRVTypeID(ExtType), false));
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}
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}
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} else {
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RegsAlreadyAddedToDT[&MI] = Reg;
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// This MI is unused and will be removed. If the MI uses
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// const_composite, it will be unused and should be removed too.
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assert(MI.getOperand(2).isReg() && "Reg operand is expected");
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MachineInstr *SrcMI = MRI.getVRegDef(MI.getOperand(2).getReg());
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if (SrcMI && isSpvIntrinsic(*SrcMI, Intrinsic::spv_const_composite))
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ToEraseComposites.push_back(SrcMI);
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}
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}
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}
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}
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for (MachineInstr *MI : ToErase) {
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Register Reg = MI->getOperand(2).getReg();
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if (RegsAlreadyAddedToDT.contains(MI))
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Reg = RegsAlreadyAddedToDT[MI];
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auto *RC = MRI.getRegClassOrNull(MI->getOperand(0).getReg());
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if (!MRI.getRegClassOrNull(Reg) && RC)
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MRI.setRegClass(Reg, RC);
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MRI.replaceRegWith(MI->getOperand(0).getReg(), Reg);
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MI->eraseFromParent();
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}
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for (MachineInstr *MI : ToEraseComposites)
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MI->eraseFromParent();
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}
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static void
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foldConstantsIntoIntrinsics(MachineFunction &MF,
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const SmallSet<Register, 4> &TrackedConstRegs) {
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SmallVector<MachineInstr *, 10> ToErase;
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const unsigned AssignNameOperandShift = 2;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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if (!isSpvIntrinsic(MI, Intrinsic::spv_assign_name))
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continue;
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unsigned NumOp = MI.getNumExplicitDefs() + AssignNameOperandShift;
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while (MI.getOperand(NumOp).isReg()) {
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MachineOperand &MOp = MI.getOperand(NumOp);
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MachineInstr *ConstMI = MRI.getVRegDef(MOp.getReg());
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assert(ConstMI->getOpcode() == TargetOpcode::G_CONSTANT);
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MI.removeOperand(NumOp);
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MI.addOperand(MachineOperand::CreateImm(
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ConstMI->getOperand(1).getCImm()->getZExtValue()));
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Register DefReg = ConstMI->getOperand(0).getReg();
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if (MRI.use_empty(DefReg) && !TrackedConstRegs.contains(DefReg))
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ToErase.push_back(ConstMI);
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}
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}
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}
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for (MachineInstr *MI : ToErase)
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MI->eraseFromParent();
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}
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static MachineInstr *findAssignTypeInstr(Register Reg,
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MachineRegisterInfo *MRI) {
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for (MachineRegisterInfo::use_instr_iterator I = MRI->use_instr_begin(Reg),
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IE = MRI->use_instr_end();
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I != IE; ++I) {
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MachineInstr *UseMI = &*I;
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if ((isSpvIntrinsic(*UseMI, Intrinsic::spv_assign_ptr_type) ||
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isSpvIntrinsic(*UseMI, Intrinsic::spv_assign_type)) &&
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UseMI->getOperand(1).getReg() == Reg)
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return UseMI;
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}
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return nullptr;
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}
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static void insertBitcasts(MachineFunction &MF, SPIRVGlobalRegistry *GR,
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MachineIRBuilder MIB) {
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// Get access to information about available extensions
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const SPIRVSubtarget *ST =
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static_cast<const SPIRVSubtarget *>(&MIB.getMF().getSubtarget());
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SmallVector<MachineInstr *, 10> ToErase;
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for (MachineBasicBlock &MBB : MF) {
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for (MachineInstr &MI : MBB) {
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if (!isSpvIntrinsic(MI, Intrinsic::spv_bitcast) &&
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!isSpvIntrinsic(MI, Intrinsic::spv_ptrcast))
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continue;
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assert(MI.getOperand(2).isReg());
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MIB.setInsertPt(*MI.getParent(), MI);
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ToErase.push_back(&MI);
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if (isSpvIntrinsic(MI, Intrinsic::spv_bitcast)) {
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MIB.buildBitcast(MI.getOperand(0).getReg(), MI.getOperand(2).getReg());
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continue;
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}
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Register Def = MI.getOperand(0).getReg();
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Register Source = MI.getOperand(2).getReg();
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Type *ElemTy = getMDOperandAsType(MI.getOperand(3).getMetadata(), 0);
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SPIRVType *BaseTy = GR->getOrCreateSPIRVType(ElemTy, MIB);
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SPIRVType *AssignedPtrType = GR->getOrCreateSPIRVPointerType(
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BaseTy, MI, *MF.getSubtarget<SPIRVSubtarget>().getInstrInfo(),
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addressSpaceToStorageClass(MI.getOperand(4).getImm(), *ST));
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// If the ptrcast would be redundant, replace all uses with the source
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// register.
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if (GR->getSPIRVTypeForVReg(Source) == AssignedPtrType) {
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// Erase Def's assign type instruction if we are going to replace Def.
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if (MachineInstr *AssignMI = findAssignTypeInstr(Def, MIB.getMRI()))
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ToErase.push_back(AssignMI);
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MIB.getMRI()->replaceRegWith(Def, Source);
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} else {
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GR->assignSPIRVTypeToVReg(AssignedPtrType, Def, MF);
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MIB.buildBitcast(Def, Source);
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}
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}
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}
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for (MachineInstr *MI : ToErase)
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MI->eraseFromParent();
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}
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// Translating GV, IRTranslator sometimes generates following IR:
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// %1 = G_GLOBAL_VALUE
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// %2 = COPY %1
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// %3 = G_ADDRSPACE_CAST %2
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//
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// or
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//
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// %1 = G_ZEXT %2
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// G_MEMCPY ... %2 ...
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//
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// New registers have no SPIRVType and no register class info.
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//
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// Set SPIRVType for GV, propagate it from GV to other instructions,
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// also set register classes.
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static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIB) {
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SPIRVType *SpvType = nullptr;
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assert(MI && "Machine instr is expected");
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if (MI->getOperand(0).isReg()) {
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Register Reg = MI->getOperand(0).getReg();
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SpvType = GR->getSPIRVTypeForVReg(Reg);
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if (!SpvType) {
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switch (MI->getOpcode()) {
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case TargetOpcode::G_CONSTANT: {
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MIB.setInsertPt(*MI->getParent(), MI);
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Type *Ty = MI->getOperand(1).getCImm()->getType();
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SpvType = GR->getOrCreateSPIRVType(Ty, MIB);
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break;
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}
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case TargetOpcode::G_GLOBAL_VALUE: {
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MIB.setInsertPt(*MI->getParent(), MI);
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const GlobalValue *Global = MI->getOperand(1).getGlobal();
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Type *ElementTy = toTypedPointer(GR->getDeducedGlobalValueType(Global));
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auto *Ty = TypedPointerType::get(ElementTy,
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Global->getType()->getAddressSpace());
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SpvType = GR->getOrCreateSPIRVType(Ty, MIB);
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break;
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}
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case TargetOpcode::G_ANYEXT:
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case TargetOpcode::G_SEXT:
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case TargetOpcode::G_ZEXT: {
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if (MI->getOperand(1).isReg()) {
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if (MachineInstr *DefInstr =
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MRI.getVRegDef(MI->getOperand(1).getReg())) {
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if (SPIRVType *Def = propagateSPIRVType(DefInstr, GR, MRI, MIB)) {
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unsigned CurrentBW = GR->getScalarOrVectorBitWidth(Def);
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unsigned ExpectedBW =
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std::max(MRI.getType(Reg).getScalarSizeInBits(), CurrentBW);
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unsigned NumElements = GR->getScalarOrVectorComponentCount(Def);
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SpvType = GR->getOrCreateSPIRVIntegerType(ExpectedBW, MIB);
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if (NumElements > 1)
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SpvType =
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GR->getOrCreateSPIRVVectorType(SpvType, NumElements, MIB);
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}
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}
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}
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break;
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}
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case TargetOpcode::G_PTRTOINT:
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SpvType = GR->getOrCreateSPIRVIntegerType(
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MRI.getType(Reg).getScalarSizeInBits(), MIB);
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break;
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case TargetOpcode::G_TRUNC:
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case TargetOpcode::G_ADDRSPACE_CAST:
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case TargetOpcode::G_PTR_ADD:
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case TargetOpcode::COPY: {
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MachineOperand &Op = MI->getOperand(1);
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MachineInstr *Def = Op.isReg() ? MRI.getVRegDef(Op.getReg()) : nullptr;
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if (Def)
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SpvType = propagateSPIRVType(Def, GR, MRI, MIB);
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break;
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}
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default:
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break;
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}
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if (SpvType)
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GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
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if (!MRI.getRegClassOrNull(Reg))
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MRI.setRegClass(Reg, &SPIRV::iIDRegClass);
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}
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}
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return SpvType;
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}
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// To support current approach and limitations wrt. bit width here we widen a
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// scalar register with a bit width greater than 1 to valid sizes and cap it to
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// 64 width.
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static void widenScalarLLTNextPow2(Register Reg, MachineRegisterInfo &MRI) {
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LLT RegType = MRI.getType(Reg);
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if (!RegType.isScalar())
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return;
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unsigned Sz = RegType.getScalarSizeInBits();
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if (Sz == 1)
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return;
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unsigned NewSz = std::min(std::max(1u << Log2_32_Ceil(Sz), 8u), 64u);
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if (NewSz != Sz)
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MRI.setType(Reg, LLT::scalar(NewSz));
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}
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inline bool getIsFloat(SPIRVType *SpvType, const SPIRVGlobalRegistry &GR) {
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bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat;
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return IsFloat ? true
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: SpvType->getOpcode() == SPIRV::OpTypeVector &&
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GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg())
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->getOpcode() == SPIRV::OpTypeFloat;
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}
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static const TargetRegisterClass *getRegClass(SPIRVType *SpvType,
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const SPIRVGlobalRegistry &GR) {
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unsigned Opcode = SpvType->getOpcode();
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switch (Opcode) {
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case SPIRV::OpTypeFloat:
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return &SPIRV::fIDRegClass;
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case SPIRV::OpTypePointer:
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return GR.getPointerSize() == 64 ? &SPIRV::pID64RegClass
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: &SPIRV::pID32RegClass;
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case SPIRV::OpTypeVector: {
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SPIRVType *ElemType =
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GR.getSPIRVTypeForVReg(SpvType->getOperand(1).getReg());
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unsigned ElemOpcode = ElemType ? ElemType->getOpcode() : 0;
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if (ElemOpcode == SPIRV::OpTypeFloat)
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return &SPIRV::vfIDRegClass;
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if (ElemOpcode == SPIRV::OpTypePointer)
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return GR.getPointerSize() == 64 ? &SPIRV::vpID64RegClass
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: &SPIRV::vpID32RegClass;
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return &SPIRV::vIDRegClass;
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}
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}
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return &SPIRV::iIDRegClass;
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}
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static std::pair<Register, unsigned>
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createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI,
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const SPIRVGlobalRegistry &GR) {
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if (!SpvType)
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SpvType = GR.getSPIRVTypeForVReg(SrcReg);
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assert(SpvType && "VReg is expected to have SPIRV type");
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LLT NewT;
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LLT SrcLLT = MRI.getType(SrcReg);
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bool IsFloat = getIsFloat(SpvType, GR);
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auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID;
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if (SrcLLT.isPointer()) {
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unsigned PtrSz = GR.getPointerSize();
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NewT = LLT::pointer(0, PtrSz);
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bool IsVec = SrcLLT.isVector();
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if (IsVec)
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NewT = LLT::fixed_vector(2, NewT);
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if (PtrSz == 64)
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GetIdOp = IsVec ? SPIRV::GET_vpID64 : SPIRV::GET_pID64;
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else
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GetIdOp = IsVec ? SPIRV::GET_vpID32 : SPIRV::GET_pID32;
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} else if (SrcLLT.isVector()) {
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NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
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NewT = LLT::fixed_vector(2, NewT);
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GetIdOp = IsFloat ? SPIRV::GET_vfID : SPIRV::GET_vID;
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} else {
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NewT = LLT::scalar(GR.getScalarOrVectorBitWidth(SpvType));
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}
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Register IdReg = MRI.createGenericVirtualRegister(NewT);
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MRI.setRegClass(IdReg, getRegClass(SpvType, GR));
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return {IdReg, GetIdOp};
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}
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// Insert ASSIGN_TYPE instuction between Reg and its definition, set NewReg as
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// a dst of the definition, assign SPIRVType to both registers. If SpvType is
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// provided, use it as SPIRVType in ASSIGN_TYPE, otherwise create it from Ty.
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// It's used also in SPIRVBuiltins.cpp.
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// TODO: maybe move to SPIRVUtils.
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namespace llvm {
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Register insertAssignInstr(Register Reg, Type *Ty, SPIRVType *SpvType,
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SPIRVGlobalRegistry *GR, MachineIRBuilder &MIB,
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MachineRegisterInfo &MRI) {
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MachineInstr *Def = MRI.getVRegDef(Reg);
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assert((Ty || SpvType) && "Either LLVM or SPIRV type is expected.");
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MIB.setInsertPt(*Def->getParent(),
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(Def->getNextNode() ? Def->getNextNode()->getIterator()
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: Def->getParent()->end()));
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SpvType = SpvType ? SpvType : GR->getOrCreateSPIRVType(Ty, MIB);
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Register NewReg = MRI.createGenericVirtualRegister(MRI.getType(Reg));
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if (auto *RC = MRI.getRegClassOrNull(Reg)) {
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MRI.setRegClass(NewReg, RC);
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} else {
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auto RegClass = getRegClass(SpvType, *GR);
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MRI.setRegClass(NewReg, RegClass);
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MRI.setRegClass(Reg, RegClass);
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}
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GR->assignSPIRVTypeToVReg(SpvType, Reg, MIB.getMF());
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// This is to make it convenient for Legalizer to get the SPIRVType
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// when processing the actual MI (i.e. not pseudo one).
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GR->assignSPIRVTypeToVReg(SpvType, NewReg, MIB.getMF());
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// Copy MIFlags from Def to ASSIGN_TYPE instruction. It's required to keep
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// the flags after instruction selection.
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const uint32_t Flags = Def->getFlags();
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MIB.buildInstr(SPIRV::ASSIGN_TYPE)
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.addDef(Reg)
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.addUse(NewReg)
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.addUse(GR->getSPIRVTypeID(SpvType))
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.setMIFlags(Flags);
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Def->getOperand(0).setReg(NewReg);
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return NewReg;
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}
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void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
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MachineRegisterInfo &MRI, SPIRVGlobalRegistry *GR) {
|
|
assert(MI.getNumDefs() > 0 && MRI.hasOneUse(MI.getOperand(0).getReg()));
|
|
MachineInstr &AssignTypeInst =
|
|
*(MRI.use_instr_begin(MI.getOperand(0).getReg()));
|
|
auto NewReg =
|
|
createNewIdReg(nullptr, MI.getOperand(0).getReg(), MRI, *GR).first;
|
|
AssignTypeInst.getOperand(1).setReg(NewReg);
|
|
MI.getOperand(0).setReg(NewReg);
|
|
MIB.setInsertPt(*MI.getParent(),
|
|
(MI.getNextNode() ? MI.getNextNode()->getIterator()
|
|
: MI.getParent()->end()));
|
|
for (auto &Op : MI.operands()) {
|
|
if (!Op.isReg() || Op.isDef())
|
|
continue;
|
|
auto IdOpInfo = createNewIdReg(nullptr, Op.getReg(), MRI, *GR);
|
|
MIB.buildInstr(IdOpInfo.second).addDef(IdOpInfo.first).addUse(Op.getReg());
|
|
Op.setReg(IdOpInfo.first);
|
|
}
|
|
}
|
|
} // namespace llvm
|
|
|
|
static void
|
|
generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR,
|
|
MachineIRBuilder MIB,
|
|
DenseMap<MachineInstr *, Type *> &TargetExtConstTypes) {
|
|
// Get access to information about available extensions
|
|
const SPIRVSubtarget *ST =
|
|
static_cast<const SPIRVSubtarget *>(&MIB.getMF().getSubtarget());
|
|
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
SmallVector<MachineInstr *, 10> ToErase;
|
|
DenseMap<MachineInstr *, Register> RegsAlreadyAddedToDT;
|
|
|
|
for (MachineBasicBlock *MBB : post_order(&MF)) {
|
|
if (MBB->empty())
|
|
continue;
|
|
|
|
bool ReachedBegin = false;
|
|
for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
|
|
!ReachedBegin;) {
|
|
MachineInstr &MI = *MII;
|
|
unsigned MIOp = MI.getOpcode();
|
|
|
|
// validate bit width of scalar registers
|
|
for (const auto &MOP : MI.operands())
|
|
if (MOP.isReg())
|
|
widenScalarLLTNextPow2(MOP.getReg(), MRI);
|
|
|
|
if (isSpvIntrinsic(MI, Intrinsic::spv_assign_ptr_type)) {
|
|
Register Reg = MI.getOperand(1).getReg();
|
|
MIB.setInsertPt(*MI.getParent(), MI.getIterator());
|
|
Type *ElementTy = getMDOperandAsType(MI.getOperand(2).getMetadata(), 0);
|
|
SPIRVType *BaseTy = GR->getOrCreateSPIRVType(ElementTy, MIB);
|
|
SPIRVType *AssignedPtrType = GR->getOrCreateSPIRVPointerType(
|
|
BaseTy, MI, *MF.getSubtarget<SPIRVSubtarget>().getInstrInfo(),
|
|
addressSpaceToStorageClass(MI.getOperand(3).getImm(), *ST));
|
|
MachineInstr *Def = MRI.getVRegDef(Reg);
|
|
assert(Def && "Expecting an instruction that defines the register");
|
|
// G_GLOBAL_VALUE already has type info.
|
|
if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE &&
|
|
Def->getOpcode() != SPIRV::ASSIGN_TYPE)
|
|
insertAssignInstr(Reg, nullptr, AssignedPtrType, GR, MIB,
|
|
MF.getRegInfo());
|
|
ToErase.push_back(&MI);
|
|
} else if (isSpvIntrinsic(MI, Intrinsic::spv_assign_type)) {
|
|
Register Reg = MI.getOperand(1).getReg();
|
|
Type *Ty = getMDOperandAsType(MI.getOperand(2).getMetadata(), 0);
|
|
MachineInstr *Def = MRI.getVRegDef(Reg);
|
|
assert(Def && "Expecting an instruction that defines the register");
|
|
// G_GLOBAL_VALUE already has type info.
|
|
if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE &&
|
|
Def->getOpcode() != SPIRV::ASSIGN_TYPE)
|
|
insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MF.getRegInfo());
|
|
ToErase.push_back(&MI);
|
|
} else if (MIOp == TargetOpcode::G_CONSTANT ||
|
|
MIOp == TargetOpcode::G_FCONSTANT ||
|
|
MIOp == TargetOpcode::G_BUILD_VECTOR) {
|
|
// %rc = G_CONSTANT ty Val
|
|
// ===>
|
|
// %cty = OpType* ty
|
|
// %rctmp = G_CONSTANT ty Val
|
|
// %rc = ASSIGN_TYPE %rctmp, %cty
|
|
Register Reg = MI.getOperand(0).getReg();
|
|
bool NeedAssignType = true;
|
|
if (MRI.hasOneUse(Reg)) {
|
|
MachineInstr &UseMI = *MRI.use_instr_begin(Reg);
|
|
if (isSpvIntrinsic(UseMI, Intrinsic::spv_assign_type) ||
|
|
isSpvIntrinsic(UseMI, Intrinsic::spv_assign_name))
|
|
continue;
|
|
}
|
|
Type *Ty = nullptr;
|
|
if (MIOp == TargetOpcode::G_CONSTANT) {
|
|
auto TargetExtIt = TargetExtConstTypes.find(&MI);
|
|
Ty = TargetExtIt == TargetExtConstTypes.end()
|
|
? MI.getOperand(1).getCImm()->getType()
|
|
: TargetExtIt->second;
|
|
const ConstantInt *OpCI = MI.getOperand(1).getCImm();
|
|
Register PrimaryReg = GR->find(OpCI, &MF);
|
|
if (!PrimaryReg.isValid()) {
|
|
GR->add(OpCI, &MF, Reg);
|
|
} else if (PrimaryReg != Reg &&
|
|
MRI.getType(Reg) == MRI.getType(PrimaryReg)) {
|
|
auto *RCReg = MRI.getRegClassOrNull(Reg);
|
|
auto *RCPrimary = MRI.getRegClassOrNull(PrimaryReg);
|
|
if (!RCReg || RCPrimary == RCReg) {
|
|
RegsAlreadyAddedToDT[&MI] = PrimaryReg;
|
|
ToErase.push_back(&MI);
|
|
NeedAssignType = false;
|
|
}
|
|
}
|
|
} else if (MIOp == TargetOpcode::G_FCONSTANT) {
|
|
Ty = MI.getOperand(1).getFPImm()->getType();
|
|
} else {
|
|
assert(MIOp == TargetOpcode::G_BUILD_VECTOR);
|
|
Type *ElemTy = nullptr;
|
|
MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg());
|
|
assert(ElemMI);
|
|
|
|
if (ElemMI->getOpcode() == TargetOpcode::G_CONSTANT) {
|
|
ElemTy = ElemMI->getOperand(1).getCImm()->getType();
|
|
} else if (ElemMI->getOpcode() == TargetOpcode::G_FCONSTANT) {
|
|
ElemTy = ElemMI->getOperand(1).getFPImm()->getType();
|
|
} else {
|
|
// There may be a case when we already know Reg's type.
|
|
MachineInstr *NextMI = MI.getNextNode();
|
|
if (!NextMI || NextMI->getOpcode() != SPIRV::ASSIGN_TYPE ||
|
|
NextMI->getOperand(1).getReg() != Reg)
|
|
llvm_unreachable("Unexpected opcode");
|
|
}
|
|
if (ElemTy)
|
|
Ty = VectorType::get(
|
|
ElemTy, MI.getNumExplicitOperands() - MI.getNumExplicitDefs(),
|
|
false);
|
|
else
|
|
NeedAssignType = false;
|
|
}
|
|
if (NeedAssignType)
|
|
insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MRI);
|
|
} else if (MIOp == TargetOpcode::G_GLOBAL_VALUE) {
|
|
propagateSPIRVType(&MI, GR, MRI, MIB);
|
|
}
|
|
|
|
if (MII == Begin)
|
|
ReachedBegin = true;
|
|
else
|
|
--MII;
|
|
}
|
|
}
|
|
for (MachineInstr *MI : ToErase) {
|
|
auto It = RegsAlreadyAddedToDT.find(MI);
|
|
if (RegsAlreadyAddedToDT.contains(MI))
|
|
MRI.replaceRegWith(MI->getOperand(0).getReg(), It->second);
|
|
MI->eraseFromParent();
|
|
}
|
|
|
|
// Address the case when IRTranslator introduces instructions with new
|
|
// registers without SPIRVType associated.
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
for (MachineInstr &MI : MBB) {
|
|
switch (MI.getOpcode()) {
|
|
case TargetOpcode::G_TRUNC:
|
|
case TargetOpcode::G_ANYEXT:
|
|
case TargetOpcode::G_SEXT:
|
|
case TargetOpcode::G_ZEXT:
|
|
case TargetOpcode::G_PTRTOINT:
|
|
case TargetOpcode::COPY:
|
|
case TargetOpcode::G_ADDRSPACE_CAST:
|
|
propagateSPIRVType(&MI, GR, MRI, MIB);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Defined in SPIRVLegalizerInfo.cpp.
|
|
extern bool isTypeFoldingSupported(unsigned Opcode);
|
|
|
|
static void processInstrsWithTypeFolding(MachineFunction &MF,
|
|
SPIRVGlobalRegistry *GR,
|
|
MachineIRBuilder MIB) {
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
for (MachineInstr &MI : MBB) {
|
|
if (isTypeFoldingSupported(MI.getOpcode()))
|
|
processInstr(MI, MIB, MRI, GR);
|
|
}
|
|
}
|
|
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
for (MachineInstr &MI : MBB) {
|
|
// We need to rewrite dst types for ASSIGN_TYPE instrs to be able
|
|
// to perform tblgen'erated selection and we can't do that on Legalizer
|
|
// as it operates on gMIR only.
|
|
if (MI.getOpcode() != SPIRV::ASSIGN_TYPE)
|
|
continue;
|
|
Register SrcReg = MI.getOperand(1).getReg();
|
|
unsigned Opcode = MRI.getVRegDef(SrcReg)->getOpcode();
|
|
if (!isTypeFoldingSupported(Opcode))
|
|
continue;
|
|
Register DstReg = MI.getOperand(0).getReg();
|
|
// Don't need to reset type of register holding constant and used in
|
|
// G_ADDRSPACE_CAST, since it breaks legalizer.
|
|
if (Opcode == TargetOpcode::G_CONSTANT && MRI.hasOneUse(DstReg)) {
|
|
MachineInstr &UseMI = *MRI.use_instr_begin(DstReg);
|
|
if (UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
|
|
continue;
|
|
}
|
|
if (MRI.getType(DstReg).isPointer())
|
|
MRI.setType(DstReg, LLT::pointer(0, GR->getPointerSize()));
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
insertInlineAsmProcess(MachineFunction &MF, SPIRVGlobalRegistry *GR,
|
|
const SPIRVSubtarget &ST, MachineIRBuilder MIRBuilder,
|
|
const SmallVector<MachineInstr *> &ToProcess) {
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
Register AsmTargetReg;
|
|
for (unsigned i = 0, Sz = ToProcess.size(); i + 1 < Sz; i += 2) {
|
|
MachineInstr *I1 = ToProcess[i], *I2 = ToProcess[i + 1];
|
|
assert(isSpvIntrinsic(*I1, Intrinsic::spv_inline_asm) && I2->isInlineAsm());
|
|
MIRBuilder.setInsertPt(*I1->getParent(), *I1);
|
|
|
|
if (!AsmTargetReg.isValid()) {
|
|
// define vendor specific assembly target or dialect
|
|
AsmTargetReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
|
|
MRI.setRegClass(AsmTargetReg, &SPIRV::iIDRegClass);
|
|
auto AsmTargetMIB =
|
|
MIRBuilder.buildInstr(SPIRV::OpAsmTargetINTEL).addDef(AsmTargetReg);
|
|
addStringImm(ST.getTargetTripleAsStr(), AsmTargetMIB);
|
|
GR->add(AsmTargetMIB.getInstr(), &MF, AsmTargetReg);
|
|
}
|
|
|
|
// create types
|
|
const MDNode *IAMD = I1->getOperand(1).getMetadata();
|
|
FunctionType *FTy = cast<FunctionType>(getMDOperandAsType(IAMD, 0));
|
|
SmallVector<SPIRVType *, 4> ArgTypes;
|
|
for (const auto &ArgTy : FTy->params())
|
|
ArgTypes.push_back(GR->getOrCreateSPIRVType(ArgTy, MIRBuilder));
|
|
SPIRVType *RetType =
|
|
GR->getOrCreateSPIRVType(FTy->getReturnType(), MIRBuilder);
|
|
SPIRVType *FuncType = GR->getOrCreateOpTypeFunctionWithArgs(
|
|
FTy, RetType, ArgTypes, MIRBuilder);
|
|
|
|
// define vendor specific assembly instructions string
|
|
Register AsmReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
|
|
MRI.setRegClass(AsmReg, &SPIRV::iIDRegClass);
|
|
auto AsmMIB = MIRBuilder.buildInstr(SPIRV::OpAsmINTEL)
|
|
.addDef(AsmReg)
|
|
.addUse(GR->getSPIRVTypeID(RetType))
|
|
.addUse(GR->getSPIRVTypeID(FuncType))
|
|
.addUse(AsmTargetReg);
|
|
// inline asm string:
|
|
addStringImm(I2->getOperand(InlineAsm::MIOp_AsmString).getSymbolName(),
|
|
AsmMIB);
|
|
// inline asm constraint string:
|
|
addStringImm(cast<MDString>(I1->getOperand(2).getMetadata()->getOperand(0))
|
|
->getString(),
|
|
AsmMIB);
|
|
GR->add(AsmMIB.getInstr(), &MF, AsmReg);
|
|
|
|
// calls the inline assembly instruction
|
|
unsigned ExtraInfo = I2->getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
|
|
if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
|
|
MIRBuilder.buildInstr(SPIRV::OpDecorate)
|
|
.addUse(AsmReg)
|
|
.addImm(static_cast<uint32_t>(SPIRV::Decoration::SideEffectsINTEL));
|
|
Register DefReg;
|
|
SmallVector<unsigned, 4> Ops;
|
|
unsigned StartOp = InlineAsm::MIOp_FirstOperand,
|
|
AsmDescOp = InlineAsm::MIOp_FirstOperand;
|
|
unsigned I2Sz = I2->getNumOperands();
|
|
for (unsigned Idx = StartOp; Idx != I2Sz; ++Idx) {
|
|
const MachineOperand &MO = I2->getOperand(Idx);
|
|
if (MO.isMetadata())
|
|
continue;
|
|
if (Idx == AsmDescOp && MO.isImm()) {
|
|
// compute the index of the next operand descriptor
|
|
const InlineAsm::Flag F(MO.getImm());
|
|
AsmDescOp += 1 + F.getNumOperandRegisters();
|
|
} else {
|
|
if (MO.isReg() && MO.isDef())
|
|
DefReg = MO.getReg();
|
|
else
|
|
Ops.push_back(Idx);
|
|
}
|
|
}
|
|
if (!DefReg.isValid()) {
|
|
DefReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
|
|
MRI.setRegClass(DefReg, &SPIRV::iIDRegClass);
|
|
SPIRVType *VoidType = GR->getOrCreateSPIRVType(
|
|
Type::getVoidTy(MF.getFunction().getContext()), MIRBuilder);
|
|
GR->assignSPIRVTypeToVReg(VoidType, DefReg, MF);
|
|
}
|
|
auto AsmCall = MIRBuilder.buildInstr(SPIRV::OpAsmCallINTEL)
|
|
.addDef(DefReg)
|
|
.addUse(GR->getSPIRVTypeID(RetType))
|
|
.addUse(AsmReg);
|
|
unsigned IntrIdx = 2;
|
|
for (unsigned Idx : Ops) {
|
|
++IntrIdx;
|
|
const MachineOperand &MO = I2->getOperand(Idx);
|
|
if (MO.isReg())
|
|
AsmCall.addUse(MO.getReg());
|
|
else
|
|
AsmCall.addUse(I1->getOperand(IntrIdx).getReg());
|
|
}
|
|
}
|
|
for (MachineInstr *MI : ToProcess)
|
|
MI->eraseFromParent();
|
|
}
|
|
|
|
static void insertInlineAsm(MachineFunction &MF, SPIRVGlobalRegistry *GR,
|
|
const SPIRVSubtarget &ST,
|
|
MachineIRBuilder MIRBuilder) {
|
|
SmallVector<MachineInstr *> ToProcess;
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
for (MachineInstr &MI : MBB) {
|
|
if (isSpvIntrinsic(MI, Intrinsic::spv_inline_asm) ||
|
|
MI.getOpcode() == TargetOpcode::INLINEASM)
|
|
ToProcess.push_back(&MI);
|
|
}
|
|
}
|
|
if (ToProcess.size() == 0)
|
|
return;
|
|
|
|
if (!ST.canUseExtension(SPIRV::Extension::SPV_INTEL_inline_assembly))
|
|
report_fatal_error("Inline assembly instructions require the "
|
|
"following SPIR-V extension: SPV_INTEL_inline_assembly",
|
|
false);
|
|
|
|
insertInlineAsmProcess(MF, GR, ST, MIRBuilder, ToProcess);
|
|
}
|
|
|
|
static void insertSpirvDecorations(MachineFunction &MF, MachineIRBuilder MIB) {
|
|
SmallVector<MachineInstr *, 10> ToErase;
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
for (MachineInstr &MI : MBB) {
|
|
if (!isSpvIntrinsic(MI, Intrinsic::spv_assign_decoration))
|
|
continue;
|
|
MIB.setInsertPt(*MI.getParent(), MI);
|
|
buildOpSpirvDecorations(MI.getOperand(1).getReg(), MIB,
|
|
MI.getOperand(2).getMetadata());
|
|
ToErase.push_back(&MI);
|
|
}
|
|
}
|
|
for (MachineInstr *MI : ToErase)
|
|
MI->eraseFromParent();
|
|
}
|
|
|
|
// Find basic blocks of the switch and replace registers in spv_switch() by its
|
|
// MBB equivalent.
|
|
static void processSwitches(MachineFunction &MF, SPIRVGlobalRegistry *GR,
|
|
MachineIRBuilder MIB) {
|
|
DenseMap<const BasicBlock *, MachineBasicBlock *> BB2MBB;
|
|
SmallVector<std::pair<MachineInstr *, SmallVector<MachineInstr *, 8>>>
|
|
Switches;
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
BB2MBB[MBB.getBasicBlock()] = &MBB;
|
|
for (MachineInstr &MI : MBB) {
|
|
if (!isSpvIntrinsic(MI, Intrinsic::spv_switch))
|
|
continue;
|
|
// Calls to spv_switch intrinsics representing IR switches.
|
|
SmallVector<MachineInstr *, 8> NewOps;
|
|
for (unsigned i = 2; i < MI.getNumOperands(); ++i) {
|
|
Register Reg = MI.getOperand(i).getReg();
|
|
if (i % 2 == 1) {
|
|
MachineInstr *ConstInstr = getDefInstrMaybeConstant(Reg, &MRI);
|
|
NewOps.push_back(ConstInstr);
|
|
} else {
|
|
MachineInstr *BuildMBB = MRI.getVRegDef(Reg);
|
|
assert(BuildMBB &&
|
|
BuildMBB->getOpcode() == TargetOpcode::G_BLOCK_ADDR &&
|
|
BuildMBB->getOperand(1).isBlockAddress() &&
|
|
BuildMBB->getOperand(1).getBlockAddress());
|
|
NewOps.push_back(BuildMBB);
|
|
}
|
|
}
|
|
Switches.push_back(std::make_pair(&MI, NewOps));
|
|
}
|
|
}
|
|
|
|
SmallPtrSet<MachineInstr *, 8> ToEraseMI;
|
|
for (auto &SwIt : Switches) {
|
|
MachineInstr &MI = *SwIt.first;
|
|
SmallVector<MachineInstr *, 8> &Ins = SwIt.second;
|
|
SmallVector<MachineOperand, 8> NewOps;
|
|
for (unsigned i = 0; i < Ins.size(); ++i) {
|
|
if (Ins[i]->getOpcode() == TargetOpcode::G_BLOCK_ADDR) {
|
|
BasicBlock *CaseBB =
|
|
Ins[i]->getOperand(1).getBlockAddress()->getBasicBlock();
|
|
auto It = BB2MBB.find(CaseBB);
|
|
if (It == BB2MBB.end())
|
|
report_fatal_error("cannot find a machine basic block by a basic "
|
|
"block in a switch statement");
|
|
NewOps.push_back(MachineOperand::CreateMBB(It->second));
|
|
MI.getParent()->addSuccessor(It->second);
|
|
ToEraseMI.insert(Ins[i]);
|
|
} else {
|
|
NewOps.push_back(
|
|
MachineOperand::CreateCImm(Ins[i]->getOperand(1).getCImm()));
|
|
}
|
|
}
|
|
for (unsigned i = MI.getNumOperands() - 1; i > 1; --i)
|
|
MI.removeOperand(i);
|
|
for (auto &MO : NewOps)
|
|
MI.addOperand(MO);
|
|
if (MachineInstr *Next = MI.getNextNode()) {
|
|
if (isSpvIntrinsic(*Next, Intrinsic::spv_track_constant)) {
|
|
ToEraseMI.insert(Next);
|
|
Next = MI.getNextNode();
|
|
}
|
|
if (Next && Next->getOpcode() == TargetOpcode::G_BRINDIRECT)
|
|
ToEraseMI.insert(Next);
|
|
}
|
|
}
|
|
|
|
// If we just delete G_BLOCK_ADDR instructions with BlockAddress operands,
|
|
// this leaves their BasicBlock counterparts in a "address taken" status. This
|
|
// would make AsmPrinter to generate a series of unneeded labels of a "Address
|
|
// of block that was removed by CodeGen" kind. Let's first ensure that we
|
|
// don't have a dangling BlockAddress constants by zapping the BlockAddress
|
|
// nodes, and only after that proceed with erasing G_BLOCK_ADDR instructions.
|
|
Constant *Replacement =
|
|
ConstantInt::get(Type::getInt32Ty(MF.getFunction().getContext()), 1);
|
|
for (MachineInstr *BlockAddrI : ToEraseMI) {
|
|
if (BlockAddrI->getOpcode() == TargetOpcode::G_BLOCK_ADDR) {
|
|
BlockAddress *BA = const_cast<BlockAddress *>(
|
|
BlockAddrI->getOperand(1).getBlockAddress());
|
|
BA->replaceAllUsesWith(
|
|
ConstantExpr::getIntToPtr(Replacement, BA->getType()));
|
|
BA->destroyConstant();
|
|
}
|
|
BlockAddrI->eraseFromParent();
|
|
}
|
|
}
|
|
|
|
static bool isImplicitFallthrough(MachineBasicBlock &MBB) {
|
|
if (MBB.empty())
|
|
return true;
|
|
|
|
// Branching SPIR-V intrinsics are not detected by this generic method.
|
|
// Thus, we can only trust negative result.
|
|
if (!MBB.canFallThrough())
|
|
return false;
|
|
|
|
// Otherwise, we must manually check if we have a SPIR-V intrinsic which
|
|
// prevent an implicit fallthrough.
|
|
for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend();
|
|
It != E; ++It) {
|
|
if (isSpvIntrinsic(*It, Intrinsic::spv_switch))
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
static void removeImplicitFallthroughs(MachineFunction &MF,
|
|
MachineIRBuilder MIB) {
|
|
// It is valid for MachineBasicBlocks to not finish with a branch instruction.
|
|
// In such cases, they will simply fallthrough their immediate successor.
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
if (!isImplicitFallthrough(MBB))
|
|
continue;
|
|
|
|
assert(std::distance(MBB.successors().begin(), MBB.successors().end()) ==
|
|
1);
|
|
MIB.setInsertPt(MBB, MBB.end());
|
|
MIB.buildBr(**MBB.successors().begin());
|
|
}
|
|
}
|
|
|
|
bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) {
|
|
// Initialize the type registry.
|
|
const SPIRVSubtarget &ST = MF.getSubtarget<SPIRVSubtarget>();
|
|
SPIRVGlobalRegistry *GR = ST.getSPIRVGlobalRegistry();
|
|
GR->setCurrentFunc(MF);
|
|
MachineIRBuilder MIB(MF);
|
|
// a registry of target extension constants
|
|
DenseMap<MachineInstr *, Type *> TargetExtConstTypes;
|
|
// to keep record of tracked constants
|
|
SmallSet<Register, 4> TrackedConstRegs;
|
|
addConstantsToTrack(MF, GR, ST, TargetExtConstTypes, TrackedConstRegs);
|
|
foldConstantsIntoIntrinsics(MF, TrackedConstRegs);
|
|
insertBitcasts(MF, GR, MIB);
|
|
generateAssignInstrs(MF, GR, MIB, TargetExtConstTypes);
|
|
processSwitches(MF, GR, MIB);
|
|
processInstrsWithTypeFolding(MF, GR, MIB);
|
|
removeImplicitFallthroughs(MF, MIB);
|
|
insertSpirvDecorations(MF, MIB);
|
|
insertInlineAsm(MF, GR, ST, MIB);
|
|
|
|
return true;
|
|
}
|
|
|
|
INITIALIZE_PASS(SPIRVPreLegalizer, DEBUG_TYPE, "SPIRV pre legalizer", false,
|
|
false)
|
|
|
|
char SPIRVPreLegalizer::ID = 0;
|
|
|
|
FunctionPass *llvm::createSPIRVPreLegalizerPass() {
|
|
return new SPIRVPreLegalizer();
|
|
}
|