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3d7662142d
AArch32/Armv8A introduced the performance deprecation of certain patterns of IT instructions. After some debate internal to ARM, this is now being reverted; i.e. no IT instruction patterns are performance deprecated anymore, as the perfomance degredation is not significant enough. This reverts the following: "ARMv8-A deprecates some uses of the T32 IT instruction. All uses of IT that apply to instructions other than a single subsequent 16-bit instruction from a restricted set are deprecated, as are explicit references to the PC within that single 16-bit instruction. This permits the non-deprecated forms of IT and subsequent instructions to be treated as a single 32-bit conditional instruction." The deprecation no longer applies, but the behaviour may be controlled by the -arm-restrict-it and -arm-no-restrict-it command-line options, with the latter being the default. No warnings about complex IT blocks will be generated. Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D118044
390 lines
12 KiB
LLVM
390 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=CHECK-V8 %s
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; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck -check-prefix=CHECK-RESTRICT-IT %s
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define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
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; CHECK-LABEL: t1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ldr r3, LCPI0_0
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; CHECK-NEXT: cmp r0, #0
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; CHECK-NEXT: LPC0_0:
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; CHECK-NEXT: add r3, pc
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; CHECK-NEXT: str r3, [r2]
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; CHECK-NEXT: mov.w r2, #1
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; CHECK-NEXT: it eq
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; CHECK-NEXT: moveq.w r2, #-1
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; CHECK-NEXT: Ltmp0: @ Block address taken
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; CHECK-NEXT: @ %bb.1: @ %common.ret
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; CHECK-NEXT: adds r0, r1, r2
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.2:
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; CHECK-NEXT: .data_region
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; CHECK-NEXT: LCPI0_0:
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; CHECK-NEXT: .long Ltmp0-(LPC0_0+4)
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; CHECK-NEXT: .end_data_region
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;
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; CHECK-V8-LABEL: t1:
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; CHECK-V8: @ %bb.0:
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; CHECK-V8-NEXT: ldr r3, .LCPI0_0
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; CHECK-V8-NEXT: cmp r0, #0
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; CHECK-V8-NEXT: str r3, [r2]
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; CHECK-V8-NEXT: mov.w r2, #1
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; CHECK-V8-NEXT: it eq
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; CHECK-V8-NEXT: moveq.w r2, #-1
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; CHECK-V8-NEXT: .Ltmp0: @ Block address taken
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; CHECK-V8-NEXT: @ %bb.1: @ %common.ret
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; CHECK-V8-NEXT: adds r0, r1, r2
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; CHECK-V8-NEXT: bx lr
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; CHECK-V8-NEXT: .p2align 2
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; CHECK-V8-NEXT: @ %bb.2:
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; CHECK-V8-NEXT: .LCPI0_0:
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; CHECK-V8-NEXT: .long .Ltmp0
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;
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; CHECK-RESTRICT-IT-LABEL: t1:
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; CHECK-RESTRICT-IT: @ %bb.0:
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; CHECK-RESTRICT-IT-NEXT: ldr r3, .LCPI0_0
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; CHECK-RESTRICT-IT-NEXT: str r3, [r2]
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; CHECK-RESTRICT-IT-NEXT: movs r2, #1
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; CHECK-RESTRICT-IT-NEXT: cmp r0, #0
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; CHECK-RESTRICT-IT-NEXT: it eq
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; CHECK-RESTRICT-IT-NEXT: moveq.w r2, #-1
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; CHECK-RESTRICT-IT-NEXT: .Ltmp0: @ Block address taken
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; CHECK-RESTRICT-IT-NEXT: @ %bb.1: @ %common.ret
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; CHECK-RESTRICT-IT-NEXT: adds r0, r1, r2
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; CHECK-RESTRICT-IT-NEXT: bx lr
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; CHECK-RESTRICT-IT-NEXT: .p2align 2
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; CHECK-RESTRICT-IT-NEXT: @ %bb.2:
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; CHECK-RESTRICT-IT-NEXT: .LCPI0_0:
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; CHECK-RESTRICT-IT-NEXT: .long .Ltmp0
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store i8* blockaddress(@t1, %cond_true), i8** %retaddr
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%tmp2 = icmp eq i32 %a, 0
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br i1 %tmp2, label %cond_false, label %cond_true
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cond_true:
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%tmp5 = add i32 %b, 1
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ret i32 %tmp5
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cond_false:
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%tmp7 = add i32 %b, -1
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ret i32 %tmp7
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}
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define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) {
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; CHECK-LABEL: t2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: ldr.w r9, [sp]
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; CHECK-NEXT: add r0, r1
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; CHECK-NEXT: ldr.w r12, LCPI1_0
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; CHECK-NEXT: cmp r3, #3
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; CHECK-NEXT: LPC1_0:
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; CHECK-NEXT: add r12, pc
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; CHECK-NEXT: str.w r12, [r9]
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; CHECK-NEXT: it gt
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; CHECK-NEXT: bxgt lr
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; CHECK-NEXT: LBB1_1:
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; CHECK-NEXT: cmp r2, #10
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; CHECK-NEXT: ble LBB1_3
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; CHECK-NEXT: Ltmp1: @ Block address taken
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; CHECK-NEXT: @ %bb.2: @ %cond_true
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; CHECK-NEXT: add r0, r2
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; CHECK-NEXT: subs r0, r0, r3
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; CHECK-NEXT: LBB1_3: @ %common.ret
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.4:
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; CHECK-NEXT: .data_region
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; CHECK-NEXT: LCPI1_0:
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; CHECK-NEXT: .long Ltmp1-(LPC1_0+4)
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; CHECK-NEXT: .end_data_region
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;
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; CHECK-V8-LABEL: t2:
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; CHECK-V8: @ %bb.0:
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; CHECK-V8-NEXT: push {r7, lr}
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; CHECK-V8-NEXT: ldr.w r12, [sp, #8]
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; CHECK-V8-NEXT: add r0, r1
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; CHECK-V8-NEXT: ldr.w lr, .LCPI1_0
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; CHECK-V8-NEXT: cmp r3, #3
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; CHECK-V8-NEXT: str.w lr, [r12]
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; CHECK-V8-NEXT: it gt
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; CHECK-V8-NEXT: popgt {r7, pc}
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; CHECK-V8-NEXT: .LBB1_1:
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; CHECK-V8-NEXT: cmp r2, #10
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; CHECK-V8-NEXT: ble .LBB1_3
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; CHECK-V8-NEXT: .Ltmp1: @ Block address taken
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; CHECK-V8-NEXT: @ %bb.2: @ %cond_true
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; CHECK-V8-NEXT: add r0, r2
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; CHECK-V8-NEXT: subs r0, r0, r3
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; CHECK-V8-NEXT: .LBB1_3: @ %common.ret
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; CHECK-V8-NEXT: pop {r7, pc}
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; CHECK-V8-NEXT: .p2align 2
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; CHECK-V8-NEXT: @ %bb.4:
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; CHECK-V8-NEXT: .LCPI1_0:
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; CHECK-V8-NEXT: .long .Ltmp1
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;
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; CHECK-RESTRICT-IT-LABEL: t2:
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; CHECK-RESTRICT-IT: @ %bb.0:
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; CHECK-RESTRICT-IT-NEXT: push {r7, lr}
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; CHECK-RESTRICT-IT-NEXT: ldr.w r12, [sp, #8]
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; CHECK-RESTRICT-IT-NEXT: add r0, r1
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; CHECK-RESTRICT-IT-NEXT: ldr.w lr, .LCPI1_0
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; CHECK-RESTRICT-IT-NEXT: cmp r3, #3
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; CHECK-RESTRICT-IT-NEXT: str.w lr, [r12]
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; CHECK-RESTRICT-IT-NEXT: bgt .LBB1_3
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; CHECK-RESTRICT-IT-NEXT: @ %bb.1:
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; CHECK-RESTRICT-IT-NEXT: cmp r2, #10
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; CHECK-RESTRICT-IT-NEXT: ble .LBB1_3
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; CHECK-RESTRICT-IT-NEXT: .Ltmp1: @ Block address taken
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; CHECK-RESTRICT-IT-NEXT: @ %bb.2: @ %cond_true
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; CHECK-RESTRICT-IT-NEXT: add r0, r2
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; CHECK-RESTRICT-IT-NEXT: subs r0, r0, r3
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; CHECK-RESTRICT-IT-NEXT: .LBB1_3: @ %common.ret
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; CHECK-RESTRICT-IT-NEXT: pop {r7, pc}
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; CHECK-RESTRICT-IT-NEXT: .p2align 2
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; CHECK-RESTRICT-IT-NEXT: @ %bb.4:
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; CHECK-RESTRICT-IT-NEXT: .LCPI1_0:
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; CHECK-RESTRICT-IT-NEXT: .long .Ltmp1
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store i8* blockaddress(@t2, %cond_true), i8** %retaddr
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%tmp2 = icmp sgt i32 %c, 10
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%tmp5 = icmp slt i32 %d, 4
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%tmp8 = and i1 %tmp5, %tmp2
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%tmp13 = add i32 %b, %a
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br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock
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cond_true:
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%tmp15 = add i32 %tmp13, %c
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%tmp1821 = sub i32 %tmp15, %d
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ret i32 %tmp1821
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UnifiedReturnBlock:
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ret i32 %tmp13
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}
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define hidden fastcc void @t3(i8** %retaddr, i1 %tst, i8* %p8) {
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; CHECK-LABEL: t3:
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; CHECK: @ %bb.0: @ %bb
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; CHECK-NEXT: ldr r1, LCPI2_0
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; CHECK-NEXT: LPC2_0:
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; CHECK-NEXT: add r1, pc
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; CHECK-NEXT: str r1, [r0]
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; CHECK-NEXT: Ltmp2: @ Block address taken
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; CHECK-NEXT: @ %bb.1: @ %common.ret
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.2:
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; CHECK-NEXT: .data_region
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; CHECK-NEXT: LCPI2_0:
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; CHECK-NEXT: .long Ltmp2-(LPC2_0+4)
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; CHECK-NEXT: .end_data_region
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;
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; CHECK-V8-LABEL: t3:
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; CHECK-V8: @ %bb.0: @ %bb
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; CHECK-V8-NEXT: ldr r1, .LCPI2_0
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; CHECK-V8-NEXT: str r1, [r0]
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; CHECK-V8-NEXT: .Ltmp2: @ Block address taken
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; CHECK-V8-NEXT: @ %bb.1: @ %common.ret
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; CHECK-V8-NEXT: bx lr
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; CHECK-V8-NEXT: .p2align 2
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; CHECK-V8-NEXT: @ %bb.2:
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; CHECK-V8-NEXT: .LCPI2_0:
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; CHECK-V8-NEXT: .long .Ltmp2
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;
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; CHECK-RESTRICT-IT-LABEL: t3:
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; CHECK-RESTRICT-IT: @ %bb.0: @ %bb
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; CHECK-RESTRICT-IT-NEXT: ldr r1, .LCPI2_0
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; CHECK-RESTRICT-IT-NEXT: str r1, [r0]
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; CHECK-RESTRICT-IT-NEXT: .Ltmp2: @ Block address taken
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; CHECK-RESTRICT-IT-NEXT: @ %bb.1: @ %common.ret
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; CHECK-RESTRICT-IT-NEXT: bx lr
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; CHECK-RESTRICT-IT-NEXT: .p2align 2
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; CHECK-RESTRICT-IT-NEXT: @ %bb.2:
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; CHECK-RESTRICT-IT-NEXT: .LCPI2_0:
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; CHECK-RESTRICT-IT-NEXT: .long .Ltmp2
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bb:
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store i8* blockaddress(@t3, %KBBlockZero_return_1), i8** %retaddr
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br i1 %tst, label %bb77, label %bb7.i
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bb7.i: ; preds = %bb35
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br label %bb2.i
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KBBlockZero_return_1: ; preds = %KBBlockZero.exit
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ret void
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KBBlockZero_return_0: ; preds = %KBBlockZero.exit
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ret void
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bb77: ; preds = %bb26, %bb12, %bb
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ret void
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bb2.i: ; preds = %bb6.i350, %bb7.i
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br i1 %tst, label %bb6.i350, label %KBBlockZero.exit
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bb6.i350: ; preds = %bb2.i
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br label %bb2.i
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KBBlockZero.exit: ; preds = %bb2.i
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indirectbr i8* %p8, [label %KBBlockZero_return_1, label %KBBlockZero_return_0]
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}
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@foo = global i32 ()* null
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define i32 @t4(i32 %x, i32 ()* %p_foo) {
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; CHECK-LABEL: t4:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r4, lr}
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; CHECK-NEXT: mov r4, r0
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; CHECK-NEXT: cmp r0, #59
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; CHECK-NEXT: ittt gt
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; CHECK-NEXT: mvngt r0, #119
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; CHECK-NEXT: addgt r0, r4
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; CHECK-NEXT: popgt {r4, pc}
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; CHECK-NEXT: LBB3_1: @ %if.then
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; CHECK-NEXT: blx r1
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; CHECK-NEXT: mov.w r0, #-1
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; CHECK-NEXT: add r0, r4
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; CHECK-NEXT: pop {r4, pc}
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;
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; CHECK-V8-LABEL: t4:
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; CHECK-V8: @ %bb.0: @ %entry
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; CHECK-V8-NEXT: push {r4, lr}
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; CHECK-V8-NEXT: mov r4, r0
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; CHECK-V8-NEXT: cmp r0, #59
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; CHECK-V8-NEXT: bgt .LBB3_2
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; CHECK-V8-NEXT: @ %bb.1: @ %if.then
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; CHECK-V8-NEXT: blx r1
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; CHECK-V8-NEXT: mov.w r0, #-1
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; CHECK-V8-NEXT: add r0, r4
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; CHECK-V8-NEXT: pop {r4, pc}
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; CHECK-V8-NEXT: .LBB3_2:
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; CHECK-V8-NEXT: mvn r0, #119
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; CHECK-V8-NEXT: add r0, r4
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; CHECK-V8-NEXT: pop {r4, pc}
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;
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; CHECK-RESTRICT-IT-LABEL: t4:
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; CHECK-RESTRICT-IT: @ %bb.0: @ %entry
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; CHECK-RESTRICT-IT-NEXT: push {r4, lr}
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; CHECK-RESTRICT-IT-NEXT: mov r4, r0
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; CHECK-RESTRICT-IT-NEXT: cmp r0, #59
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; CHECK-RESTRICT-IT-NEXT: bgt .LBB3_2
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; CHECK-RESTRICT-IT-NEXT: @ %bb.1: @ %if.then
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; CHECK-RESTRICT-IT-NEXT: blx r1
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; CHECK-RESTRICT-IT-NEXT: mov.w r0, #-1
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; CHECK-RESTRICT-IT-NEXT: add r0, r4
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; CHECK-RESTRICT-IT-NEXT: pop {r4, pc}
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; CHECK-RESTRICT-IT-NEXT: .LBB3_2:
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; CHECK-RESTRICT-IT-NEXT: mvn r0, #119
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; CHECK-RESTRICT-IT-NEXT: add r0, r4
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; CHECK-RESTRICT-IT-NEXT: pop {r4, pc}
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entry:
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%cmp = icmp slt i32 %x, 60
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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%tmp.2 = call i32 %p_foo()
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%sub = add nsw i32 %x, -1
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br label %return
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if.else: ; preds = %entry
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%sub1 = add nsw i32 %x, -120
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br label %return
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return: ; preds = %if.end5, %if.then4, %if.then
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%retval.0 = phi i32 [ %sub, %if.then ], [ %sub1, %if.else ]
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ret i32 %retval.0
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}
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; If-converter was checking for the wrong predicate subsumes pattern when doing
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; nested predicates.
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; E.g., Let A be a basic block that flows conditionally into B and B be a
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; predicated block.
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; B can be predicated with A.BrToBPredicate into A iff B.Predicate is less
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; "permissive" than A.BrToBPredicate, i.e., iff A.BrToBPredicate subsumes
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; B.Predicate.
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define i32 @wrapDistance(i32 %tx, i32 %sx, i32 %w) {
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; CHECK-LABEL: wrapDistance:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: cmp r1, #59
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; CHECK-NEXT: itt le
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; CHECK-NEXT: suble r0, r2, #1
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; CHECK-NEXT: bxle lr
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; CHECK-NEXT: LBB4_1: @ %if.else
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; CHECK-NEXT: subs r2, #120
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: bge LBB4_3
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; CHECK-NEXT: @ %bb.2: @ %if.else
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; CHECK-NEXT: cmp r0, #119
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; CHECK-NEXT: itt le
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; CHECK-NEXT: addle r0, r1, #1
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; CHECK-NEXT: bxle lr
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; CHECK-NEXT: LBB4_3: @ %if.end5
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; CHECK-NEXT: subs r0, r1, r0
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; CHECK-NEXT: bx lr
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;
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; CHECK-V8-LABEL: wrapDistance:
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; CHECK-V8: @ %bb.0: @ %entry
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; CHECK-V8-NEXT: cmp r1, #59
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; CHECK-V8-NEXT: itt le
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; CHECK-V8-NEXT: suble r0, r2, #1
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; CHECK-V8-NEXT: bxle lr
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; CHECK-V8-NEXT: .LBB4_1: @ %if.else
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; CHECK-V8-NEXT: subs r2, #120
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; CHECK-V8-NEXT: cmp r2, r1
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; CHECK-V8-NEXT: bge .LBB4_3
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; CHECK-V8-NEXT: @ %bb.2: @ %if.else
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; CHECK-V8-NEXT: cmp r0, #119
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; CHECK-V8-NEXT: itt le
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; CHECK-V8-NEXT: addle r0, r1, #1
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; CHECK-V8-NEXT: bxle lr
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; CHECK-V8-NEXT: .LBB4_3: @ %if.end5
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; CHECK-V8-NEXT: subs r0, r1, r0
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; CHECK-V8-NEXT: bx lr
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;
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; CHECK-RESTRICT-IT-LABEL: wrapDistance:
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; CHECK-RESTRICT-IT: @ %bb.0: @ %entry
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; CHECK-RESTRICT-IT-NEXT: cmp r1, #59
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; CHECK-RESTRICT-IT-NEXT: bgt .LBB4_2
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; CHECK-RESTRICT-IT-NEXT: @ %bb.1: @ %if.then
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; CHECK-RESTRICT-IT-NEXT: subs r0, r2, #1
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; CHECK-RESTRICT-IT-NEXT: bx lr
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; CHECK-RESTRICT-IT-NEXT: .LBB4_2: @ %if.else
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; CHECK-RESTRICT-IT-NEXT: subs r2, #120
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; CHECK-RESTRICT-IT-NEXT: cmp r2, r1
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; CHECK-RESTRICT-IT-NEXT: bge .LBB4_5
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; CHECK-RESTRICT-IT-NEXT: @ %bb.3: @ %if.else
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; CHECK-RESTRICT-IT-NEXT: cmp r0, #119
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; CHECK-RESTRICT-IT-NEXT: bgt .LBB4_5
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; CHECK-RESTRICT-IT-NEXT: @ %bb.4: @ %if.then4
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; CHECK-RESTRICT-IT-NEXT: adds r0, r1, #1
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; CHECK-RESTRICT-IT-NEXT: bx lr
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; CHECK-RESTRICT-IT-NEXT: .LBB4_5: @ %if.end5
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; CHECK-RESTRICT-IT-NEXT: subs r0, r1, r0
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; CHECK-RESTRICT-IT-NEXT: bx lr
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entry:
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%cmp = icmp slt i32 %sx, 60
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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%sub = add nsw i32 %w, -1
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br label %return
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if.else: ; preds = %entry
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%sub1 = add nsw i32 %w, -120
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%cmp2 = icmp slt i32 %sub1, %sx
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%cmp3 = icmp slt i32 %tx, 120
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%or.cond = and i1 %cmp2, %cmp3
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br i1 %or.cond, label %if.then4, label %if.end5
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|
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if.then4: ; preds = %if.else
|
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%add = add nsw i32 %sx, 1
|
|
br label %return
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|
|
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if.end5: ; preds = %if.else
|
|
%sub6 = sub nsw i32 %sx, %tx
|
|
br label %return
|
|
|
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return: ; preds = %if.end5, %if.then4, %if.then
|
|
%retval.0 = phi i32 [ %sub, %if.then ], [ %add, %if.then4 ], [ %sub6, %if.end5 ]
|
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ret i32 %retval.0
|
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}
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