mirror of
https://github.com/llvm/llvm-project.git
synced 2025-04-28 14:36:08 +00:00
81 lines
3.0 KiB
C++
81 lines
3.0 KiB
C++
//===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "AMDGPUGlobalISelUtils.h"
|
|
#include "GCNSubtarget.h"
|
|
#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
|
|
#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
|
|
#include "llvm/CodeGenTypes/LowLevelType.h"
|
|
#include "llvm/IR/Constants.h"
|
|
|
|
using namespace llvm;
|
|
using namespace MIPatternMatch;
|
|
|
|
std::pair<Register, unsigned>
|
|
AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg,
|
|
GISelKnownBits *KnownBits, bool CheckNUW) {
|
|
MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
|
|
if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
|
|
unsigned Offset;
|
|
const MachineOperand &Op = Def->getOperand(1);
|
|
if (Op.isImm())
|
|
Offset = Op.getImm();
|
|
else
|
|
Offset = Op.getCImm()->getZExtValue();
|
|
|
|
return std::pair(Register(), Offset);
|
|
}
|
|
|
|
int64_t Offset;
|
|
if (Def->getOpcode() == TargetOpcode::G_ADD) {
|
|
// A 32-bit (address + offset) should not cause unsigned 32-bit integer
|
|
// wraparound, because s_load instructions perform the addition in 64 bits.
|
|
if (CheckNUW && !Def->getFlag(MachineInstr::NoUWrap)) {
|
|
assert(MRI.getType(Reg).getScalarSizeInBits() == 32);
|
|
return std::pair(Reg, 0);
|
|
}
|
|
// TODO: Handle G_OR used for add case
|
|
if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
|
|
return std::pair(Def->getOperand(1).getReg(), Offset);
|
|
|
|
// FIXME: matcher should ignore copies
|
|
if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
|
|
return std::pair(Def->getOperand(1).getReg(), Offset);
|
|
}
|
|
|
|
Register Base;
|
|
if (KnownBits && mi_match(Reg, MRI, m_GOr(m_Reg(Base), m_ICst(Offset))) &&
|
|
KnownBits->maskedValueIsZero(Base, APInt(32, Offset)))
|
|
return std::pair(Base, Offset);
|
|
|
|
// Handle G_PTRTOINT (G_PTR_ADD base, const) case
|
|
if (Def->getOpcode() == TargetOpcode::G_PTRTOINT) {
|
|
MachineInstr *Base;
|
|
if (mi_match(Def->getOperand(1).getReg(), MRI,
|
|
m_GPtrAdd(m_MInstr(Base), m_ICst(Offset)))) {
|
|
// If Base was int converted to pointer, simply return int and offset.
|
|
if (Base->getOpcode() == TargetOpcode::G_INTTOPTR)
|
|
return std::pair(Base->getOperand(1).getReg(), Offset);
|
|
|
|
// Register returned here will be of pointer type.
|
|
return std::pair(Base->getOperand(0).getReg(), Offset);
|
|
}
|
|
}
|
|
|
|
return std::pair(Reg, 0);
|
|
}
|
|
|
|
bool AMDGPU::hasAtomicFaddRtnForTy(const GCNSubtarget &Subtarget,
|
|
const LLT &Ty) {
|
|
if (Ty == LLT::scalar(32))
|
|
return Subtarget.hasAtomicFaddRtnInsts();
|
|
if (Ty == LLT::fixed_vector(2, 16) || Ty == LLT::scalar(64))
|
|
return Subtarget.hasGFX90AInsts();
|
|
return false;
|
|
}
|