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Some opcodes in generic MIR represent calls to intrinsics, where the intrinsic ID is the first non-def operand to the instruction. These are now represented as a subclass of GenericMachineInstr, and the method MachineInstr::getIntrinsicID() is now moved to this subclass GIntrinsic. Some target-defined instructions behave like GMIR intrinsics, and have an Intrinsic::ID operand. But they should not be recognized as generic intrinsics, and should not use GIntrinsic::getIntrinsicID(). Separated these out by introducing a new AMDGPU::getIntrinsicID(). Reviewed By: arsenm, Pierre-vh Differential Revision: https://reviews.llvm.org/D155556 This restores commit baa3386edb11a2f9bcadda8cf58d56f3707c39fa. Originally reverted in d0f7850b01cf17e50a4f4b00e3b84dded94df6b8.
98 lines
2.4 KiB
C++
98 lines
2.4 KiB
C++
//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Contains the definition of a TargetInstrInfo class that is common
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/// to all AMD GPUs.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
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#include "Utils/AMDGPUBaseInfo.h"
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namespace llvm {
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class GCNSubtarget;
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class MachineMemOperand;
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class MachineInstr;
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class AMDGPUInstrInfo {
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public:
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explicit AMDGPUInstrInfo(const GCNSubtarget &st);
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static bool isUniformMMO(const MachineMemOperand *MMO);
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};
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namespace AMDGPU {
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/// Return the intrinsic ID for opcodes with the G_AMDGPU_INTRIN_ prefix.
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///
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/// These opcodes have an Intrinsic::ID operand similar to a GIntrinsic. But
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/// they are not actual instances of GIntrinsics, so we cannot use
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/// GIntrinsic::getIntrinsicID() on them.
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unsigned getIntrinsicID(const MachineInstr &I);
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struct RsrcIntrinsic {
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unsigned Intr;
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uint8_t RsrcArg;
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bool IsImage;
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};
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const RsrcIntrinsic *lookupRsrcIntrinsic(unsigned Intr);
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struct D16ImageDimIntrinsic {
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unsigned Intr;
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unsigned D16HelperIntr;
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};
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const D16ImageDimIntrinsic *lookupD16ImageDimIntrinsic(unsigned Intr);
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struct ImageDimIntrinsicInfo {
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unsigned Intr;
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unsigned BaseOpcode;
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MIMGDim Dim;
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uint8_t NumOffsetArgs;
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uint8_t NumBiasArgs;
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uint8_t NumZCompareArgs;
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uint8_t NumGradients;
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uint8_t NumDmask;
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uint8_t NumData;
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uint8_t NumVAddrs;
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uint8_t NumArgs;
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uint8_t DMaskIndex;
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uint8_t VAddrStart;
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uint8_t OffsetIndex;
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uint8_t BiasIndex;
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uint8_t ZCompareIndex;
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uint8_t GradientStart;
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uint8_t CoordStart;
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uint8_t LodIndex;
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uint8_t MipIndex;
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uint8_t VAddrEnd;
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uint8_t RsrcIndex;
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uint8_t SampIndex;
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uint8_t UnormIndex;
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uint8_t TexFailCtrlIndex;
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uint8_t CachePolicyIndex;
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uint8_t BiasTyArg;
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uint8_t GradientTyArg;
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uint8_t CoordTyArg;
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};
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const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr);
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const ImageDimIntrinsicInfo *
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getImageDimIntrinsicByBaseOpcode(unsigned BaseOpcode, unsigned Dim);
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} // end AMDGPU namespace
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} // End llvm namespace
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#endif
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