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These both perform conditional subtraction, returning the minuend and zero respectively, if the difference is negative.
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============================
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LLVM |release| Release Notes
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============================
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.. contents::
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:local:
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.. only:: PreRelease
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.. warning::
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These are in-progress notes for the upcoming LLVM |version| release.
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Release notes for previous releases can be found on
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`the Download Page <https://releases.llvm.org/download.html>`_.
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Introduction
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============
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This document contains the release notes for the LLVM Compiler Infrastructure,
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release |release|. Here we describe the status of LLVM, including major improvements
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from the previous release, improvements in various subprojects of LLVM, and
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some of the current users of the code. All LLVM releases may be downloaded
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from the `LLVM releases web site <https://llvm.org/releases/>`_.
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For more information about LLVM, including information about the latest
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release, please check out the `main LLVM web site <https://llvm.org/>`_. If you
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have questions or comments, the `Discourse forums
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<https://discourse.llvm.org>`_ is a good place to ask
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them.
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Note that if you are reading this file from a Git checkout or the main
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LLVM web page, this document applies to the *next* release, not the current
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one. To see the release notes for a specific release, please see the `releases
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page <https://llvm.org/releases/>`_.
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Non-comprehensive list of changes in this release
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=================================================
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.. NOTE
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For small 1-3 sentence descriptions, just add an entry at the end of
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this list. If your description won't fit comfortably in one bullet
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point (e.g. maybe you would like to give an example of the
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functionality, or simply have a lot to talk about), see the `NOTE` below
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for adding a new subsection.
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* ...
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Update on required toolchains to build LLVM
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-------------------------------------------
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Changes to the LLVM IR
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----------------------
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* The ``x86_mmx`` IR type has been removed. It will be translated to
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the standard vector type ``<1 x i64>`` in bitcode upgrade.
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* Renamed ``llvm.experimental.stepvector`` intrinsic to ``llvm.stepvector``.
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* Added ``usub_cond`` and ``usub_sat`` operations to ``atomicrmw``.
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Changes to LLVM infrastructure
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------------------------------
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Changes to building LLVM
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------------------------
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Changes to TableGen
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-------------------
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Changes to Interprocedural Optimizations
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----------------------------------------
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Changes to the AArch64 Backend
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------------------------------
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* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
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the required alignment space with a sequence of `0x0` bytes (the requested
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fill value) rather than NOPs.
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Changes to the AMDGPU Backend
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-----------------------------
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* Removed ``llvm.amdgcn.flat.atomic.fadd`` and
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``llvm.amdgcn.global.atomic.fadd`` intrinsics. Users should use the
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:ref:`atomicrmw <i_atomicrmw>` instruction with `fadd` and
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addrspace(0) or addrspace(1) instead.
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Changes to the ARM Backend
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--------------------------
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* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
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the required alignment space with a sequence of `0x0` bytes (the requested
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fill value) rather than NOPs.
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Changes to the AVR Backend
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--------------------------
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Changes to the DirectX Backend
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------------------------------
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Changes to the Hexagon Backend
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------------------------------
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Changes to the LoongArch Backend
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--------------------------------
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Changes to the MIPS Backend
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---------------------------
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Changes to the PowerPC Backend
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------------------------------
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Changes to the RISC-V Backend
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-----------------------------
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* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
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the required alignment space with a sequence of `0x0` bytes (the requested
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fill value) rather than NOPs.
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* Added Syntacore SCR4 and SCR5 CPUs: ``-mcpu=syntacore-scr4/5-rv32/64``
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* ``-mcpu=sifive-p470`` was added.
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* Added Hazard3 CPU as taped out for RP2350: ``-mcpu=rp2350-hazard3`` (32-bit
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only).
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* Fixed length vector support using RVV instructions now requires VLEN>=64. This
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means Zve32x and Zve32f will also require Zvl64b. The prior support was
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largely untested.
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* The ``Zvbc32e`` and ``Zvkgs`` extensions are now supported experimentally.
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* Added ``Smctr`` and ``Ssctr`` extensions.
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Changes to the WebAssembly Backend
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----------------------------------
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Changes to the Windows Target
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-----------------------------
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Changes to the X86 Backend
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--------------------------
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* `.balign N, 0x90`, `.p2align N, 0x90`, and `.align N, 0x90` in code sections
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now fill the required alignment space with repeating `0x90` bytes, rather than
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using optimised NOP filling. Optimised NOP filling fills the space with NOP
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instructions of various widths, not just those that use the `0x90` byte
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encoding. To use optimised NOP filling in a code section, leave off the
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"fillval" argument, i.e. `.balign N`, `.p2align N` or `.align N` respectively.
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* Due to the removal of the ``x86_mmx`` IR type, functions with
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``x86_mmx`` arguments or return values will use a different,
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incompatible, calling convention ABI. Such functions are not
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generally seen in the wild (Clang never generates them!), so this is
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not expected to result in real-world compatibility problems.
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* Support ISA of ``AVX10.2-256`` and ``AVX10.2-512``.
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Changes to the OCaml bindings
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-----------------------------
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Changes to the Python bindings
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------------------------------
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Changes to the C API
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--------------------
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* The following symbols are deleted due to the removal of the ``x86_mmx`` IR type:
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* ``LLVMX86_MMXTypeKind``
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* ``LLVMX86MMXTypeInContext``
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* ``LLVMX86MMXType``
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* The following functions are added to further support non-null-terminated strings:
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* ``LLVMGetNamedFunctionWithLength``
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* ``LLVMGetNamedGlobalWithLength``
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* The following functions are added to access the ``LLVMContextRef`` associated
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with ``LLVMValueRef`` and ``LLVMBuilderRef`` objects:
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* ``LLVMGetValueContext``
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* ``LLVMGetBuilderContext``
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* The new pass manager can now be invoked with a custom alias analysis pipeline, using
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the ``LLVMPassBuilderOptionsSetAAPipeline`` function.
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* It is now also possible to run the new pass manager on a single function, by calling
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``LLVMRunPassesOnFunction`` instead of ``LLVMRunPasses``.
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* Support for creating instructions with custom synchronization scopes has been added:
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* ``LLVMGetSyncScopeID`` to map a synchronization scope name to an ID.
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* ``LLVMBuildFenceSyncScope``, ``LLVMBuildAtomicRMWSyncScope`` and
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``LLVMBuildAtomicCmpXchgSyncScope`` versions of the existing builder functions
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with an additional synchronization scope ID parameter.
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* ``LLVMGetAtomicSyncScopeID`` and ``LLVMSetAtomicSyncScopeID`` to get and set the
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synchronization scope of any atomic instruction.
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* ``LLVMIsAtomic`` to check if an instruction is atomic, for use with the above functions.
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Because of backwards compatibility, ``LLVMIsAtomicSingleThread`` and
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``LLVMSetAtomicSingleThread`` continue to work with any instruction type.
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* The `LLVMSetPersonalityFn` and `LLVMSetInitializer` APIs now support clearing the
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personality function and initializer respectively by passing a null pointer.
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Changes to the CodeGen infrastructure
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-------------------------------------
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Changes to the Metadata Info
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---------------------------------
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Changes to the Debug Info
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---------------------------------
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Changes to the LLVM tools
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---------------------------------
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Changes to LLDB
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---------------------------------
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Changes to BOLT
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---------------------------------
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Changes to Sanitizers
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---------------------
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Other Changes
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-------------
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External Open Source Projects Using LLVM 19
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===========================================
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* A project...
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Additional Information
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======================
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A wide variety of additional information is available on the `LLVM web page
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<https://llvm.org/>`_, in particular in the `documentation
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<https://llvm.org/docs/>`_ section. The web page also contains versions of the
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API documentation which is up-to-date with the Git version of the source
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code. You can access versions of these documents specific to this release by
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going into the ``llvm/docs/`` directory in the LLVM tree.
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If you have any questions or comments about LLVM, please feel free to contact
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us via the `Discourse forums <https://discourse.llvm.org>`_.
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