mirror of
https://github.com/llvm/llvm-project.git
synced 2025-05-06 05:36:06 +00:00
1d0244aed7
Reverts 02940d6d2202. Fixes breakage in the modules build. LLVM loops cannot represent irreducible structures in the CFG. This change introduce the concept of cycles as a generalization of loops, along with a CycleInfo analysis that discovers a nested hierarchy of such cycles. This is based on Havlak (1997), Nesting of Reducible and Irreducible Loops. The cycle analysis is implemented as a generic template and then instatiated for LLVM IR and Machine IR. The template relies on a new GenericSSAContext template which must be specialized when used for each IR. This review is a restart of an older review request: https://reviews.llvm.org/D83094 Original implementation by Nicolai Hähnle <nicolai.haehnle@amd.com>, with recent refactoring by Sameer Sahasrabuddhe <sameer.sahasrabuddhe@amd.com> Differential Revision: https://reviews.llvm.org/D112696
53 lines
1.6 KiB
C++
53 lines
1.6 KiB
C++
//===- MachineSSAContext.cpp ------------------------------------*- C++ -*-===//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
/// \file
|
|
///
|
|
/// This file defines a specialization of the GenericSSAContext<X>
|
|
/// template class for Machine IR.
|
|
///
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/CodeGen/MachineSSAContext.h"
|
|
#include "llvm/CodeGen/MachineBasicBlock.h"
|
|
#include "llvm/CodeGen/MachineInstr.h"
|
|
#include "llvm/Support/raw_ostream.h"
|
|
|
|
using namespace llvm;
|
|
|
|
MachineBasicBlock *MachineSSAContext::getEntryBlock(MachineFunction &F) {
|
|
return &F.front();
|
|
}
|
|
|
|
void MachineSSAContext::setFunction(MachineFunction &Fn) {
|
|
MF = &Fn;
|
|
RegInfo = &MF->getRegInfo();
|
|
}
|
|
|
|
Printable MachineSSAContext::print(MachineBasicBlock *Block) const {
|
|
return Printable([Block](raw_ostream &Out) { Block->printName(Out); });
|
|
}
|
|
|
|
Printable MachineSSAContext::print(MachineInstr *I) const {
|
|
return Printable([I](raw_ostream &Out) { I->print(Out); });
|
|
}
|
|
|
|
Printable MachineSSAContext::print(Register Value) const {
|
|
auto *MRI = RegInfo;
|
|
return Printable([MRI, Value](raw_ostream &Out) {
|
|
Out << printReg(Value, MRI->getTargetRegisterInfo(), 0, MRI);
|
|
|
|
if (Value) {
|
|
// Try to print the definition.
|
|
if (auto *Instr = MRI->getUniqueVRegDef(Value)) {
|
|
Out << ": ";
|
|
Instr->print(Out);
|
|
}
|
|
}
|
|
});
|
|
}
|