Durgadoss R 2feced1df0

[MLIR][NVVM] Add tcgen05 wait/fence Ops (#126265) ...

PR #126091 adds intrinsics for tcgen05
wait/fence/commit operations. This patch
adds NVVM Dialect Ops for them.

Signed-off-by: Durgadoss R <durgadossr@nvidia.com>

2025-02-08 21:34:40 +05:30

..

Analysis

[mlir] Add a null pointer check in symbol lookup (#115165)

2024-11-12 23:31:25 +01:00

Bytecode

[MLIR] print/parse resource handle key quoted and escaped (#119746)

2025-02-04 13:49:15 -07:00

CAPI

[mlir][llvmir][reland] expose Type(To/From)LLVMIRTranslator C API (#125110)

2025-01-31 10:40:56 -05:00

Conversion

[TOSA] Fix negate maxValue computation (#126295)

2025-02-08 09:23:32 +00:00

Dialect

[MLIR][Affine] Fix private memref creation bug in affine fusion (#126028)

2025-02-08 08:35:10 +05:30

Examples

[mlir][LLVM] Switch undef for poison for uninitialized values (#125629)

2025-02-06 12:49:30 -06:00

Integration

[mlir][Vector] Add UB conversions to different tests and pipelines (#125145)

2025-02-03 17:13:53 -08:00

Interfaces

[mlir][affine]introducing new symbol rules that the result of a Pure operation that whose operands are valid symbolic identifiers (#118478)

2025-01-17 21:21:41 +08:00

IR

[MLIR] print/parse resource handle key quoted and escaped (#119746)

2025-02-04 13:49:15 -07:00

lib

[MLIR] Support non-atomic RMW option for emulated vector stores (#124887)

2025-02-06 13:22:42 -08:00

mlir-linalg-ods-gen

…

mlir-lsp-server

…

mlir-opt

…

mlir-pdll

mlir/LogicalResult: move into llvm (#97309)

2024-07-02 10:42:33 +01:00

mlir-pdll-lsp-server

…

mlir-query

…

mlir-reduce

…

mlir-rewrite

[MLIR][BUILD] Fix Unicode build issue on Windows. (#112300)

2024-10-18 14:34:33 +08:00

mlir-runner

Revert "[mlir][math]Update convertPowfOp ExpandPatterns.cpp" (#126063)

2025-02-06 05:19:45 -08:00

mlir-tblgen

[TableGen] Add assert to validate Objects list for HwModeSelect (#123794)

2025-01-27 13:44:44 -08:00

mlir-translate

…

Pass

[mlir] Attempt to resolve edge cases in PassPipeline textual format (#118877)

2024-12-17 21:13:29 -07:00

python

[mlir] Python: Parse ModuleOp from file path (#125736)

2025-02-05 11:48:37 -08:00

Rewrite

…

Target

[MLIR][NVVM] Add tcgen05 wait/fence Ops (#126265)

2025-02-08 21:34:40 +05:30

tblgen-lsp-server

[TableGen] Do not exit in template argument check (#121636)

2025-01-06 21:06:17 +01:00

tblgen-to-irdl

[mlir][irdl] Introduce names in IRDL value lists (#123525)

2025-01-19 21:58:52 +01:00

Transforms

[ViewOpGraph] Improve GraphViz output (#125509)

2025-02-07 10:45:47 -05:00

Unit

…

APITest.h

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CMakeLists.txt

[mlir] Rename mlir-cpu-runner to mlir-runner (#123776)

2025-01-24 14:08:38 +01:00

get_darwin_real_python.py

[MLIR, Python] Make it easy to run tests with ASan on mac (#115524)

2024-11-23 01:34:03 +01:00

lit.cfg.py

MLIR: asan: Fix python tests under asan on Linux (#123303)

2025-01-29 08:36:13 +01:00

lit.site.cfg.py.in

[mlir] Rename mlir-cpu-runner to mlir-runner (#123776)

2025-01-24 14:08:38 +01:00