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304f1d59ca
This switches everything to use the memory attribute proposed in https://discourse.llvm.org/t/rfc-unify-memory-effect-attributes/65579. The old argmemonly, inaccessiblememonly and inaccessiblemem_or_argmemonly attributes are dropped. The readnone, readonly and writeonly attributes are restricted to parameters only. The old attributes are auto-upgraded both in bitcode and IR. The bitcode upgrade is a policy requirement that has to be retained indefinitely. The IR upgrade is mainly there so it's not necessary to update all tests using memory attributes in this patch, which is already large enough. We could drop that part after migrating tests, or retain it longer term, to make it easier to import IR from older LLVM versions. High-level Function/CallBase APIs like doesNotAccessMemory() or setDoesNotAccessMemory() are mapped transparently to the memory attribute. Code that directly manipulates attributes (e.g. via AttributeList) on the other hand needs to switch to working with the memory attribute instead. Differential Revision: https://reviews.llvm.org/D135780
55 lines
2.4 KiB
C++
55 lines
2.4 KiB
C++
// Test that the use of thread local variables would be wrapped by @llvm.threadlocal.address intrinsics.
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// RUN: %clang_cc1 -std=c++11 -emit-llvm -triple x86_64 -o - %s -disable-llvm-passes | FileCheck %s
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// RUN: %clang_cc1 -std=c++11 -emit-llvm -triple aarch64 -o - -O1 %s | FileCheck %s -check-prefix=CHECK-O1
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thread_local int i;
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int g() {
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i++;
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return i;
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}
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// CHECK: @i = {{.*}}thread_local global i32 0
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// CHECK: @_ZZ1fvE1j = internal thread_local global i32 0
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//
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// CHECK: @_Z1gv()
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// CHECK-NEXT: entry
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// CHECK-NEXT: %[[IA:.+]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @i)
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// CHECK-NEXT: %[[VA:.+]] = load i32, ptr %[[IA]]
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// CHECK-NEXT: %[[INC:.+]] = add nsw i32 %[[VA]], 1
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// CHECK-NEXT: store i32 %[[INC]], ptr %[[IA]], align 4
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// CHECK-NEXT: %[[IA2:.+]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @i)
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// CHECK-NEXT: %[[RET:.+]] = load i32, ptr %[[IA2]], align 4
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// CHECK-NEXT: ret i32 %[[RET]]
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//
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// CHECK: declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) #[[ATTR_NUM:.+]]
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//
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// CHECK-O1-LABEL: @_Z1gv
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: %[[I_ADDR:.+]] = {{.*}}call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @i)
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// CHECK-O1-NEXT: %[[VAL:.+]] = load i32, ptr %[[I_ADDR]]
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// CHECK-O1-NEXT: %[[INC:.+]] = add nsw i32 %[[VAL]], 1
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// CHECK-O1-NEXT: store i32 %[[INC]], ptr %[[I_ADDR]]
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// CHECK-O1-NEXT: ret i32 %[[INC]]
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int f() {
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thread_local int j = 0;
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j++;
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return j;
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}
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// CHECK: @_Z1fv()
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// CHECK-NEXT: entry
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// CHECK-NEXT: %[[JA:.+]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ1fvE1j)
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// CHECK-NEXT: %[[VA:.+]] = load i32, ptr %[[JA]]
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// CHECK-NEXT: %[[INC:.+]] = add nsw i32 %[[VA]], 1
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// CHECK-NEXT: store i32 %[[INC]], ptr %[[JA]], align 4
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// CHECK-NEXT: %[[JA2:.+]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ1fvE1j)
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// CHECK-NEXT: %[[RET:.+]] = load i32, ptr %[[JA2]], align 4
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// CHECK-NEXT: ret i32 %[[RET]]
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//
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// CHECK-O1-LABEL: @_Z1fv
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: %[[J_ADDR:.+]] = {{.*}}call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ1fvE1j)
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// CHECK-O1-NEXT: %[[VAL:.+]] = load i32, ptr %[[J_ADDR]]
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// CHECK-O1-NEXT: %[[INC:.+]] = add nsw i32 %[[VAL]], 1
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// CHECK-O1-NEXT: store i32 %[[INC]], ptr %[[J_ADDR]]
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// CHECK-O1-NEXT: ret i32 %[[INC]]
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//
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// CHECK: attributes #[[ATTR_NUM]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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