Aditi Medhane 60a8b2b1d0

[AMDGPU] Add MachineVerifier check to detect illegal copies from vector register to SGPR (#105494) ...

Addition of a check in the MachineVerifier to detect and report illegal
vector registers to SGPR copies in the AMDGPU backend, ensuring correct
code generation.
We can enforce this check only after SIFixSGPRCopies pass.
This is half-fix in the pipeline with the help of isSSA MachineFuction
property, the check is happening for passes after phi-node-elimination.

2024-09-19 13:57:44 +05:30

..

AMDGPU

[AMDGPU] Add MachineVerifier check to detect illegal copies from vector register to SGPR (#105494)

2024-09-19 13:57:44 +05:30

convergencectrl/AMDGPU

[AMDGPU,test] Change llc -march= to -mtriple=

2024-03-07 19:09:18 -08:00

copy-scalable.mir

[MachineVerifier] Fix COPY check in MachineVerifier for scalable vectors

2023-11-07 14:49:38 -08:00

generic-vreg-undef-use.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

live-ins-01.mir

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live-ins-02.mir

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live-ins-03.mir

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test_adjustsstack.mir

Reapply "Move assertion for AdjustsStack from PEI to MachineVerifier (#85698)"

2024-03-21 20:24:57 -04:00

test_copy_mismatch_types.mir

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test_copy_physregs_x86.mir

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test_copy.mir

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test_g_add.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_addrspacecast.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_assert_align.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_assert_sext_register_bank_class.mir

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test_g_assert_sext.mir

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test_g_assert_zext_register_bank_class.mir

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test_g_assert_zext.mir

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test_g_brindirect_is_indirect_branch.mir

[test] -march -> -mtriple (#67741)

2023-09-29 10:43:23 -07:00

test_g_brjt_is_indirect_branch.mir

[test] -march -> -mtriple (#67741)

2023-09-29 10:43:23 -07:00

test_g_brjt.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_bswap.mir

[GISel] Restrict G_BSWAP to multiples of 16 bits. (#70245)

2023-10-30 10:27:57 -07:00

test_g_build_vector_trunc.mir

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test_g_build_vector.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_bzero.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_concat_vectors.mir

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test_g_constant_pool.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_constant.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_dyn_stackalloc.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_extract_subvector.mir

[MachineVerifier] Improve G_EXTRACT_SUBVECTOR checking (#109202)

2024-09-18 18:29:32 -07:00

test_g_extract.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_fcmp.mir

[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

2024-04-03 15:27:15 -07:00

test_g_fconstant.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_icmp.mir

[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

2024-04-03 15:27:15 -07:00

test_g_insert_subvector.mir

[MachineVerifier] Improve checks for G_INSERT_SUBVECTOR. (#109209)

2024-09-18 18:31:16 -07:00

test_g_insert.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_inttoptr.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_invoke_region_start.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_is_fpclass.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_jump_table.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_llround.mir

llvm.lround: Update verifier to validate support of vector types. (#98950)

2024-08-20 13:24:15 -05:00

test_g_load.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_lround.mir

llvm.lround: Update verifier to validate support of vector types. (#98950)

2024-08-20 13:24:15 -05:00

test_g_memcpy_inline.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_memcpy.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_memmove.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_memset.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_merge_values.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_phi.mir

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test_g_prefetch.mir

[GlobalISel] Add G_PREFETCH (#74863)

2023-12-11 11:06:50 +00:00

test_g_ptr_add.mir

[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)

2024-03-09 09:07:22 +00:00

test_g_ptrmask.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_ptrtoint.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_rotr_rotl.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_select.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_sext_inreg.mir

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test_g_sextload.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_shift.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_shuffle_vector.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_splat_vector.mir

[GISel][RISCV] Correctly handle scalable vector shuffles of pointer vectors in IRTranslator. (#106580)

2024-08-29 12:35:50 -07:00

test_g_store.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_trunc.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_ubfx_sbfx.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_ubsantrap.mir

[GlobalISel] Introduce G_TRAP, G_DEBUGTRAP, G_UBSANTRAP (#84941)

2024-03-23 13:12:44 +01:00

test_g_unmerge_values.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_g_vscale.mir

[GlobalIsel] Fix Machine Verifier errors (#99018)

2024-07-17 06:04:46 +02:00

test_g_zextload.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_insert_subreg.mir

[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64

2023-09-29 10:13:06 -07:00

test_phis_precede_nonphis.mir

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test_uscmp.mir

[GlobalIsel] Add G_SCMP and G_UCMP instructions (#98894)

2024-07-18 16:22:37 +02:00

test_vector_reductions.mir

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verifier-generic-extend-truncate.mir

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verifier-generic-types-1.mir

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verifier-generic-types-2.mir

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verifier-phi-fail0.mir

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verifier-phi.mir

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verifier-statepoint.mir

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verify-inlineasmbr.mir

[test] Avoid writing to a potentially write-protected dir (#89242)

2024-04-20 12:26:58 +02:00

verify-regbankselected-dbg-undef-use.mir

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verify-regbankselected.mir

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verify-regops.mir

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verify-selected-dbg-undef-use.mir

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verify-selected.mir

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