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5fdd094837
In the beginning, Clang only emitted atomic IR for operations it knew the underlying microarch had instructions for, meaning it required significant knowledge of the target. Later, the backend acquired the ability to lower IR to libcalls. To avoid duplicating logic and improve logic locality, we'd like to move as much as possible to the backend. There are many ways to describe this change. For example, this change reduces the variables Clang uses to decide whether to emit libcalls or IR, down to only the atomic's size.
36 lines
1.2 KiB
C
36 lines
1.2 KiB
C
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=thumbv7m-none--eabi -target-cpu cortex-m3 | FileCheck %s
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int i;
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long long l;
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typedef enum memory_order {
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memory_order_relaxed, memory_order_consume, memory_order_acquire,
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memory_order_release, memory_order_acq_rel, memory_order_seq_cst
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} memory_order;
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void test_presence(void)
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{
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// CHECK-LABEL: @test_presence
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// CHECK: atomicrmw add ptr {{.*}} seq_cst, align 4
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__atomic_fetch_add(&i, 1, memory_order_seq_cst);
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// CHECK: atomicrmw sub ptr {{.*}} seq_cst, align 4
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__atomic_fetch_sub(&i, 1, memory_order_seq_cst);
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// CHECK: load atomic i32, ptr {{.*}} seq_cst, align 4
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int r;
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__atomic_load(&i, &r, memory_order_seq_cst);
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// CHECK: store atomic i32 {{.*}} seq_cst, align 4
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r = 0;
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__atomic_store(&i, &r, memory_order_seq_cst);
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// CHECK: atomicrmw add ptr {{.*}} seq_cst, align 8
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__atomic_fetch_add(&l, 1, memory_order_seq_cst);
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// CHECK: atomicrmw sub ptr {{.*}} seq_cst, align 8
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__atomic_fetch_sub(&l, 1, memory_order_seq_cst);
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// CHECK: load atomic i64, ptr {{.*}} seq_cst, align 8
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long long rl;
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__atomic_load(&l, &rl, memory_order_seq_cst);
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// CHECK: store atomic i64 {{.*}}, ptr {{.*}} seq_cst, align 8
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rl = 0;
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__atomic_store(&l, &rl, memory_order_seq_cst);
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}
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