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168 lines
7.2 KiB
C
168 lines
7.2 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +f -target-feature +d -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 -O1 -emit-llvm -o - %s | FileCheck %s
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// REQUIRES: riscv-registered-target
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#include <riscv_vector.h>
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typedef vint32m1_t fixed_int32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vfloat64m1_t fixed_float64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vbool1_t fixed_bool1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
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typedef vbool4_t fixed_bool4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
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//===----------------------------------------------------------------------===//
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// Test caller/callee with VLST <-> VLAT
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @sizeless_callee(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 2 x i32> [[X:%.*]]
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//
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vint32m1_t sizeless_callee(vint32m1_t x) {
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return x;
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}
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// CHECK-LABEL: @fixed_caller(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 2 x i32> [[X_COERCE:%.*]]
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//
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fixed_int32m1_t fixed_caller(fixed_int32m1_t x) {
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return sizeless_callee(x);
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}
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// CHECK-LABEL: @fixed_callee(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 2 x i32> [[X_COERCE:%.*]]
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//
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fixed_int32m1_t fixed_callee(fixed_int32m1_t x) {
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return x;
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}
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// CHECK-LABEL: @sizeless_caller(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 2 x i32> [[X:%.*]]
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//
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vint32m1_t sizeless_caller(vint32m1_t x) {
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return fixed_callee(x);
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}
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//===----------------------------------------------------------------------===//
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// fixed, fixed
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @call_int32_ff(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1_COERCE:%.*]], <vscale x 2 x i32> [[OP2_COERCE:%.*]], i64 8)
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// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
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//
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fixed_int32m1_t call_int32_ff(fixed_int32m1_t op1, fixed_int32m1_t op2) {
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return __riscv_vadd(op1, op2, __riscv_v_fixed_vlen/32);
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}
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// CHECK-LABEL: @call_float64_ff(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[OP1_COERCE:%.*]], <vscale x 1 x double> [[OP2_COERCE:%.*]], i64 7, i64 4)
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// CHECK-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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fixed_float64m1_t call_float64_ff(fixed_float64m1_t op1, fixed_float64m1_t op2) {
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return __riscv_vfadd(op1, op2, __riscv_v_fixed_vlen/64);
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}
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// CHECK-LABEL: @call_bool1_ff(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[TMP0:%.*]], <vscale x 64 x i1> [[TMP1:%.*]], i64 256)
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// CHECK-NEXT: ret <vscale x 64 x i1> [[TMP2]]
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//
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fixed_bool1_t call_bool1_ff(fixed_bool1_t op1, fixed_bool1_t op2) {
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return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen);
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}
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// CHECK-LABEL: @call_bool4_ff(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[TMP0:%.*]], <vscale x 16 x i1> [[TMP1:%.*]], i64 64)
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
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//
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fixed_bool4_t call_bool4_ff(fixed_bool4_t op1, fixed_bool4_t op2) {
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return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen / 4);
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}
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//===----------------------------------------------------------------------===//
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// fixed, scalable
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @call_int32_fs(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1_COERCE:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 8)
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// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
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//
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fixed_int32m1_t call_int32_fs(fixed_int32m1_t op1, vint32m1_t op2) {
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return __riscv_vadd(op1, op2, __riscv_v_fixed_vlen/32);
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}
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// CHECK-LABEL: @call_float64_fs(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[OP1_COERCE:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 7, i64 4)
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// CHECK-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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fixed_float64m1_t call_float64_fs(fixed_float64m1_t op1, vfloat64m1_t op2) {
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return __riscv_vfadd(op1, op2, __riscv_v_fixed_vlen/64);
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}
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// CHECK-LABEL: @call_bool1_fs(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[TMP0:%.*]], <vscale x 64 x i1> [[OP2:%.*]], i64 256)
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// CHECK-NEXT: ret <vscale x 64 x i1> [[TMP1]]
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//
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fixed_bool1_t call_bool1_fs(fixed_bool1_t op1, vbool1_t op2) {
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return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen);
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}
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// CHECK-LABEL: @call_bool4_fs(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[TMP0:%.*]], <vscale x 16 x i1> [[OP2:%.*]], i64 64)
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
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//
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fixed_bool4_t call_bool4_fs(fixed_bool4_t op1, vbool4_t op2) {
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return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen / 4);
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}
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//===----------------------------------------------------------------------===//
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// scalable, scalable
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @call_int32_ss(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32.i64(<vscale x 2 x i32> poison, <vscale x 2 x i32> [[OP1:%.*]], <vscale x 2 x i32> [[OP2:%.*]], i64 8)
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// CHECK-NEXT: ret <vscale x 2 x i32> [[TMP0]]
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//
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fixed_int32m1_t call_int32_ss(vint32m1_t op1, vint32m1_t op2) {
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return __riscv_vadd(op1, op2, __riscv_v_fixed_vlen/32);
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}
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// CHECK-LABEL: @call_float64_ss(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 1 x double> @llvm.riscv.vfadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> poison, <vscale x 1 x double> [[OP1:%.*]], <vscale x 1 x double> [[OP2:%.*]], i64 7, i64 4)
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// CHECK-NEXT: ret <vscale x 1 x double> [[TMP0]]
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//
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fixed_float64m1_t call_float64_ss(vfloat64m1_t op1, vfloat64m1_t op2) {
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return __riscv_vfadd(op1, op2, __riscv_v_fixed_vlen/64);
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}
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// CHECK-LABEL: @call_bool1_ss(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP2:%.*]], i64 256)
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// CHECK-NEXT: ret <vscale x 64 x i1> [[TMP0]]
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//
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fixed_bool1_t call_bool1_ss(vbool1_t op1, vbool1_t op2) {
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return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen);
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}
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// CHECK-LABEL: @call_bool4_ss(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]], i64 64)
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
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//
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fixed_bool4_t call_bool4_ss(vbool4_t op1, vbool4_t op2) {
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return __riscv_vmand(op1, op2, __riscv_v_fixed_vlen / 4);
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}
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