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7298ae3b6d
Make sure that the result from the popcnt/ctlz/cttz intrinsics is unsigned casted to int, rather than casted as a signed value, when expanding the __builtin_popcountg/__builtin_ctzg/__builtin_clzg builtins. An example would be unsigned _BitInt(1) x = ...; int y = __builtin_popcountg(x); which previously was incorrectly expanded to %1 = call i1 @llvm.ctpop.i1(i1 %0) %cast = sext i1 %1 to i32 Since the input type is generic for those "g" versions of the builtins the intrinsic call may return a value for which the sign bit is set (that could typically for BitInt of size 1 and 2). So we need to emit a zext rather than a sext to avoid negative results.
127 lines
4.9 KiB
C
127 lines
4.9 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
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// RUN: %clang_cc1 -triple arm-unknown-unknown -O0 -std=c23 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-O0
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// RUN: %clang_cc1 -triple arm-unknown-unknown -O1 -std=c23 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-O1
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// Verify that the result from the intrinsic call is zero extended to avoid that
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// we get a negative result from popcountg/ctzg/clzg.
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_popcountg_ubi1(
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// CHECK-O0-SAME: ) #[[ATTR0:[0-9]+]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i1, align 1
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// CHECK-O0-NEXT: store i1 true, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i1, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i1 @llvm.ctpop.i1(i1 [[TMP0]])
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i1 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_popcountg_ubi1(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 1
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//
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int test_popcountg_ubi1() {
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unsigned _BitInt(1) a = 1uwb;
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return __builtin_popcountg(a);
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}
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_popcountg_ubi2(
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// CHECK-O0-SAME: ) #[[ATTR0]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i2, align 1
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// CHECK-O0-NEXT: store i2 -1, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i2, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i2 @llvm.ctpop.i2(i2 [[TMP0]])
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i2 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_popcountg_ubi2(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 2
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//
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int test_popcountg_ubi2() {
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unsigned _BitInt(2) a = 3uwb;
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return __builtin_popcountg(a);
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}
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_ctzg_ubi1(
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// CHECK-O0-SAME: ) #[[ATTR0]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i1, align 1
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// CHECK-O0-NEXT: store i1 false, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i1, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i1 @llvm.cttz.i1(i1 [[TMP0]], i1 false)
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i1 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_ctzg_ubi1(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 1
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//
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int test_ctzg_ubi1() {
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unsigned _BitInt(1) a = 0uwb;
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return __builtin_ctzg(a);
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}
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_ctzg_ubi2(
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// CHECK-O0-SAME: ) #[[ATTR0]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i2, align 1
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// CHECK-O0-NEXT: store i2 0, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i2, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i2 @llvm.cttz.i2(i2 [[TMP0]], i1 false)
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i2 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_ctzg_ubi2(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 2
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//
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int test_ctzg_ubi2() {
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unsigned _BitInt(2) a = 0uwb;
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return __builtin_ctzg(a);
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}
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_clzg_ubi1(
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// CHECK-O0-SAME: ) #[[ATTR0]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i1, align 1
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// CHECK-O0-NEXT: store i1 false, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i1, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i1 @llvm.ctlz.i1(i1 [[TMP0]], i1 false)
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i1 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_clzg_ubi1(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 1
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//
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int test_clzg_ubi1() {
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unsigned _BitInt(1) a = 0uwb;
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return __builtin_clzg(a);
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}
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// CHECK-O0-LABEL: define dso_local arm_aapcscc i32 @test_clzg_ubi2(
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// CHECK-O0-SAME: ) #[[ATTR0]] {
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// CHECK-O0-NEXT: entry:
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// CHECK-O0-NEXT: [[A:%.*]] = alloca i2, align 1
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// CHECK-O0-NEXT: store i2 0, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP0:%.*]] = load i2, ptr [[A]], align 1
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// CHECK-O0-NEXT: [[TMP1:%.*]] = call i2 @llvm.ctlz.i2(i2 [[TMP0]], i1 false)
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// CHECK-O0-NEXT: [[CAST:%.*]] = zext i2 [[TMP1]] to i32
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// CHECK-O0-NEXT: ret i32 [[CAST]]
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//
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// CHECK-O1-LABEL: define dso_local arm_aapcscc noundef i32 @test_clzg_ubi2(
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// CHECK-O1-SAME: ) local_unnamed_addr #[[ATTR0]] {
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// CHECK-O1-NEXT: entry:
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// CHECK-O1-NEXT: ret i32 2
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//
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int test_clzg_ubi2() {
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unsigned _BitInt(2) a = 0uwb;
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return __builtin_clzg(a);
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}
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