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c1a6defd9f
otherwise operator<<(const ELFSyncStream &s, RelType type) applies to non-reloc-type uint32_t, which can be confusing.
296 lines
8.5 KiB
C++
296 lines
8.5 KiB
C++
//===- AVR.cpp ------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// AVR is a Harvard-architecture 8-bit microcontroller designed for small
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// baremetal programs. All AVR-family processors have 32 8-bit registers.
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// The tiniest AVR has 32 byte RAM and 1 KiB program memory, and the largest
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// one supports up to 2^24 data address space and 2^22 code address space.
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//
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// Since it is a baremetal programming, there's usually no loader to load
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// ELF files on AVRs. You are expected to link your program against address
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// 0 and pull out a .text section from the result using objcopy, so that you
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// can write the linked code to on-chip flush memory. You can do that with
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// the following commands:
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//
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// ld.lld -Ttext=0 -o foo foo.o
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// objcopy -O binary --only-section=.text foo output.bin
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//
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// Note that the current AVR support is very preliminary so you can't
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// link any useful program yet, though.
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//
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//===----------------------------------------------------------------------===//
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#include "InputFiles.h"
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#include "Symbols.h"
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#include "Target.h"
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#include "Thunks.h"
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#include "lld/Common/ErrorHandler.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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using namespace llvm::object;
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using namespace llvm::support::endian;
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using namespace llvm::ELF;
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using namespace lld;
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using namespace lld::elf;
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namespace {
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class AVR final : public TargetInfo {
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public:
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AVR(Ctx &ctx) : TargetInfo(ctx) { needsThunks = true; }
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uint32_t calcEFlags() const override;
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RelExpr getRelExpr(RelType type, const Symbol &s,
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const uint8_t *loc) const override;
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bool needsThunk(RelExpr expr, RelType type, const InputFile *file,
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uint64_t branchAddr, const Symbol &s,
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int64_t a) const override;
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void relocate(uint8_t *loc, const Relocation &rel,
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uint64_t val) const override;
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};
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} // namespace
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RelExpr AVR::getRelExpr(RelType type, const Symbol &s,
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const uint8_t *loc) const {
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switch (type) {
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case R_AVR_6:
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case R_AVR_6_ADIW:
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case R_AVR_8:
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case R_AVR_8_LO8:
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case R_AVR_8_HI8:
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case R_AVR_8_HLO8:
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case R_AVR_16:
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case R_AVR_16_PM:
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case R_AVR_32:
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case R_AVR_LDI:
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case R_AVR_LO8_LDI:
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case R_AVR_LO8_LDI_NEG:
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case R_AVR_HI8_LDI:
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case R_AVR_HI8_LDI_NEG:
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case R_AVR_HH8_LDI_NEG:
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case R_AVR_HH8_LDI:
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case R_AVR_MS8_LDI_NEG:
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case R_AVR_MS8_LDI:
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case R_AVR_LO8_LDI_GS:
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case R_AVR_LO8_LDI_PM:
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case R_AVR_LO8_LDI_PM_NEG:
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case R_AVR_HI8_LDI_GS:
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case R_AVR_HI8_LDI_PM:
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case R_AVR_HI8_LDI_PM_NEG:
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case R_AVR_HH8_LDI_PM:
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case R_AVR_HH8_LDI_PM_NEG:
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case R_AVR_LDS_STS_16:
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case R_AVR_PORT5:
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case R_AVR_PORT6:
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case R_AVR_CALL:
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return R_ABS;
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case R_AVR_7_PCREL:
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case R_AVR_13_PCREL:
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return R_PC;
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default:
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Err(ctx) << getErrorLoc(ctx, loc) << "unknown relocation (" << type.v
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<< ") against symbol " << &s;
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return R_NONE;
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}
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}
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static void writeLDI(uint8_t *loc, uint64_t val) {
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write16le(loc, (read16le(loc) & 0xf0f0) | (val & 0xf0) << 4 | (val & 0x0f));
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}
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bool AVR::needsThunk(RelExpr expr, RelType type, const InputFile *file,
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uint64_t branchAddr, const Symbol &s, int64_t a) const {
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switch (type) {
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case R_AVR_LO8_LDI_GS:
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case R_AVR_HI8_LDI_GS:
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// A thunk is needed if the symbol's virtual address is out of range
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// [0, 0x1ffff].
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return s.getVA(ctx) >= 0x20000;
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default:
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return false;
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}
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}
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void AVR::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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switch (rel.type) {
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case R_AVR_8:
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checkUInt(ctx, loc, val, 8, rel);
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*loc = val;
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break;
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case R_AVR_8_LO8:
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checkUInt(ctx, loc, val, 32, rel);
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*loc = val & 0xff;
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break;
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case R_AVR_8_HI8:
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checkUInt(ctx, loc, val, 32, rel);
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*loc = (val >> 8) & 0xff;
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break;
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case R_AVR_8_HLO8:
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checkUInt(ctx, loc, val, 32, rel);
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*loc = (val >> 16) & 0xff;
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break;
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case R_AVR_16:
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// Note: this relocation is often used between code and data space, which
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// are 0x800000 apart in the output ELF file. The bitmask cuts off the high
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// bit.
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write16le(loc, val & 0xffff);
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break;
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case R_AVR_16_PM:
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checkAlignment(ctx, loc, val, 2, rel);
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checkUInt(ctx, loc, val >> 1, 16, rel);
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write16le(loc, val >> 1);
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break;
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case R_AVR_32:
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checkUInt(ctx, loc, val, 32, rel);
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write32le(loc, val);
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break;
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case R_AVR_LDI:
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checkUInt(ctx, loc, val, 8, rel);
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writeLDI(loc, val & 0xff);
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break;
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case R_AVR_LO8_LDI_NEG:
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writeLDI(loc, -val & 0xff);
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break;
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case R_AVR_LO8_LDI:
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writeLDI(loc, val & 0xff);
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break;
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case R_AVR_HI8_LDI_NEG:
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writeLDI(loc, (-val >> 8) & 0xff);
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break;
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case R_AVR_HI8_LDI:
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writeLDI(loc, (val >> 8) & 0xff);
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break;
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case R_AVR_HH8_LDI_NEG:
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writeLDI(loc, (-val >> 16) & 0xff);
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break;
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case R_AVR_HH8_LDI:
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writeLDI(loc, (val >> 16) & 0xff);
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break;
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case R_AVR_MS8_LDI_NEG:
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writeLDI(loc, (-val >> 24) & 0xff);
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break;
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case R_AVR_MS8_LDI:
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writeLDI(loc, (val >> 24) & 0xff);
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break;
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case R_AVR_LO8_LDI_GS:
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checkUInt(ctx, loc, val, 17, rel);
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[[fallthrough]];
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case R_AVR_LO8_LDI_PM:
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checkAlignment(ctx, loc, val, 2, rel);
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writeLDI(loc, (val >> 1) & 0xff);
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break;
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case R_AVR_HI8_LDI_GS:
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checkUInt(ctx, loc, val, 17, rel);
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[[fallthrough]];
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case R_AVR_HI8_LDI_PM:
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checkAlignment(ctx, loc, val, 2, rel);
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writeLDI(loc, (val >> 9) & 0xff);
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break;
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case R_AVR_HH8_LDI_PM:
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checkAlignment(ctx, loc, val, 2, rel);
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writeLDI(loc, (val >> 17) & 0xff);
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break;
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case R_AVR_LO8_LDI_PM_NEG:
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checkAlignment(ctx, loc, val, 2, rel);
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writeLDI(loc, (-val >> 1) & 0xff);
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break;
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case R_AVR_HI8_LDI_PM_NEG:
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checkAlignment(ctx, loc, val, 2, rel);
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writeLDI(loc, (-val >> 9) & 0xff);
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break;
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case R_AVR_HH8_LDI_PM_NEG:
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checkAlignment(ctx, loc, val, 2, rel);
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writeLDI(loc, (-val >> 17) & 0xff);
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break;
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case R_AVR_LDS_STS_16: {
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checkUInt(ctx, loc, val, 7, rel);
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const uint16_t hi = val >> 4;
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const uint16_t lo = val & 0xf;
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write16le(loc, (read16le(loc) & 0xf8f0) | ((hi << 8) | lo));
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break;
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}
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case R_AVR_PORT5:
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checkUInt(ctx, loc, val, 5, rel);
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write16le(loc, (read16le(loc) & 0xff07) | (val << 3));
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break;
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case R_AVR_PORT6:
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checkUInt(ctx, loc, val, 6, rel);
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write16le(loc, (read16le(loc) & 0xf9f0) | (val & 0x30) << 5 | (val & 0x0f));
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break;
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// Since every jump destination is word aligned we gain an extra bit
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case R_AVR_7_PCREL: {
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checkInt(ctx, loc, val - 2, 8, rel);
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checkAlignment(ctx, loc, val, 2, rel);
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const uint16_t target = (val - 2) >> 1;
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write16le(loc, (read16le(loc) & 0xfc07) | ((target & 0x7f) << 3));
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break;
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}
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case R_AVR_13_PCREL: {
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checkAlignment(ctx, loc, val, 2, rel);
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const uint16_t target = (val - 2) >> 1;
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write16le(loc, (read16le(loc) & 0xf000) | (target & 0xfff));
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break;
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}
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case R_AVR_6:
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checkInt(ctx, loc, val, 6, rel);
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write16le(loc, (read16le(loc) & 0xd3f8) | (val & 0x20) << 8 |
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(val & 0x18) << 7 | (val & 0x07));
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break;
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case R_AVR_6_ADIW:
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checkInt(ctx, loc, val, 6, rel);
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write16le(loc, (read16le(loc) & 0xff30) | (val & 0x30) << 2 | (val & 0x0F));
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break;
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case R_AVR_CALL: {
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checkAlignment(ctx, loc, val, 2, rel);
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uint16_t hi = val >> 17;
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uint16_t lo = val >> 1;
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write16le(loc, read16le(loc) | ((hi >> 1) << 4) | (hi & 1));
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write16le(loc + 2, lo);
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break;
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}
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default:
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llvm_unreachable("unknown relocation");
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}
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}
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void elf::setAVRTargetInfo(Ctx &ctx) { ctx.target.reset(new AVR(ctx)); }
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static uint32_t getEFlags(InputFile *file) {
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return cast<ObjFile<ELF32LE>>(file)->getObj().getHeader().e_flags;
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}
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uint32_t AVR::calcEFlags() const {
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assert(!ctx.objectFiles.empty());
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uint32_t flags = getEFlags(ctx.objectFiles[0]);
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bool hasLinkRelaxFlag = flags & EF_AVR_LINKRELAX_PREPARED;
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for (InputFile *f : ArrayRef(ctx.objectFiles).slice(1)) {
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uint32_t objFlags = getEFlags(f);
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if ((objFlags & EF_AVR_ARCH_MASK) != (flags & EF_AVR_ARCH_MASK))
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ErrAlways(ctx)
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<< f << ": cannot link object files with incompatible target ISA";
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if (!(objFlags & EF_AVR_LINKRELAX_PREPARED))
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hasLinkRelaxFlag = false;
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}
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if (!hasLinkRelaxFlag)
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flags &= ~EF_AVR_LINKRELAX_PREPARED;
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return flags;
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}
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