llvm-project

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History

[AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. (#130302 )

These are encoded as 8-bit fields.

2025-03-08 01:10:09 +00:00

AArch64

[AArch64] Add DC CIGDPAPA and DC CIPAPA instructions (#122718 )

2025-01-14 08:35:36 +00:00

AMDGPU

[AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. (#130302 )

2025-03-08 01:10:09 +00:00

ARC

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ARM

[llvm-mc] Don't print initial .text for disassembler

2024-12-16 23:38:48 -08:00

Hexagon

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Lanai

…

M68k

[M68k] update dissassmbly test to require atLeastM68020 for BSR32 (#119758 )

2024-12-12 13:15:43 -08:00

Mips

[test] Don't test initial ".text" in llvm-mc --disassemble output

2024-12-16 23:24:34 -08:00

MSP430

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PowerPC

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RISCV

[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504 )

2025-03-06 12:01:53 +05:30

Sparc

[NFC][SPARC] Fix typos and style mismatches

2024-06-19 21:44:48 +07:00

SystemZ

[SystemZ] Make I5 operand of R[INOX]SGB(Z)? optional (#129512 )

2025-03-04 18:53:36 +01:00

WebAssembly

[test] Don't test initial ".text" in llvm-mc --disassemble output

2024-12-16 23:24:34 -08:00

X86

[X86][AVX10.2-BF16] Remove [NE]P from intrinsic and instruction name (#123335 )

2025-01-24 15:49:28 +08:00

XCore

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Xtensa

[Xtensa] Implement Xtensa Boolean Option. (#126022 )

2025-02-21 23:52:06 +03:00