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11fbd0c6ab
My previous patch had added a couple of asserts to the disassembler. The problem with this is that the disassembler is not just used for the text section it is also used to disassemble the data section of an object where the bytes do not necessarily represent instructions. If the data in the data section happens to look like an illegal instruction then llvm-objdump will assert on data because it is finding an illegal instruction that is not actually an instruction at all. Reviewed By: nemanjai, #powerpc Differential Revision: https://reviews.llvm.org/D149711
407 lines
16 KiB
C++
407 lines
16 KiB
C++
//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/PPCMCTargetDesc.h"
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#include "TargetInfo/PowerPCTargetInfo.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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DEFINE_PPC_REGCLASSES
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#define DEBUG_TYPE "ppc-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class PPCDisassembler : public MCDisassembler {
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bool IsLittleEndian;
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public:
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PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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bool IsLittleEndian)
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: MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createPPCDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
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}
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static MCDisassembler *createPPCLEDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() {
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// Register the disassembler for each target.
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TargetRegistry::RegisterMCDisassembler(getThePPC32Target(),
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createPPCDisassembler);
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TargetRegistry::RegisterMCDisassembler(getThePPC32LETarget(),
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createPPCLEDisassembler);
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TargetRegistry::RegisterMCDisassembler(getThePPC64Target(),
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createPPCDisassembler);
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TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(),
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createPPCLEDisassembler);
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}
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static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
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uint64_t /*Address*/,
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const MCDisassembler * /*Decoder*/) {
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Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
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uint64_t /*Address*/,
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const MCDisassembler * /*Decoder*/) {
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int32_t Offset = SignExtend32<24>(Imm);
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Inst.addOperand(MCOperand::createImm(Offset));
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return MCDisassembler::Success;
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}
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// FIXME: These can be generated by TableGen from the existing register
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// encoding values!
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template <std::size_t N>
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static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
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const MCPhysReg (&Regs)[N]) {
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if (RegNo >= N)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, CRRegs);
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}
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static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, CRBITRegs);
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}
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static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, FRegs);
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}
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static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, FRegs);
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}
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static DecodeStatus DecodeFpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo > 30 || (RegNo & 1))
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return MCDisassembler::Fail;
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return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
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}
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static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VFRegs);
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}
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static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VRegs);
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}
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static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSRegs);
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}
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static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSFRegs);
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}
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static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSSRegs);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, RRegs);
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}
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static DecodeStatus
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DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
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}
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static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, XRegs);
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}
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static DecodeStatus DecodeG8pRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, XRegs);
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}
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static DecodeStatus
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DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
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}
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#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
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#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
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static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, SPERegs);
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}
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static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, ACCRegs);
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}
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static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, WACCRegs);
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}
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static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, WACC_HIRegs);
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}
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// TODO: Make this function static when the register class is used by a new
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// instruction.
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DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, DMRROWRegs);
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}
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static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, DMRROWpRegs);
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}
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static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, DMRRegs);
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}
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// TODO: Make this function static when the register class is used by a new
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// instruction.
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DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, DMRpRegs);
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}
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static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSRpRegs);
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}
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#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
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#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
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template <unsigned N>
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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if (!isUInt<N>(Imm))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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if (!isUInt<N>(Imm))
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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if (Imm != 0)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo & 1)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeDispRIXOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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// The rix displacement is an immediate shifted by 2
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Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 2)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeDispRIHashOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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// Decode the disp field for a hash store or hash check operation.
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// The field is composed of an immediate value that is 6 bits
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// and covers the range -8 to -512. The immediate is always negative and 2s
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// complement which is why we sign extend a 7 bit value.
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const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
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Inst.addOperand(MCOperand::createImm(Disp));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeDispRIX16Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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// The rix16 displacement has 12-bits which are shifted by 4.
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Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Imm << 4)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeDispSPE8Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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// Decode the dispSPE8 field, which has 5-bits, 8-byte aligned.
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uint64_t Disp = Imm & 0x1F;
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Inst.addOperand(MCOperand::createImm(Disp << 3));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeDispSPE4Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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// Decode the dispSPE8 field, which has 5-bits, 4-byte aligned.
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uint64_t Disp = Imm & 0x1F;
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Inst.addOperand(MCOperand::createImm(Disp << 2));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeDispSPE2Operand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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// Decode the dispSPE8 field, which has 5-bits, 2-byte aligned.
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uint64_t Disp = Imm & 0x1F;
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Inst.addOperand(MCOperand::createImm(Disp << 1));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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// The cr bit encoding is 0x80 >> cr_reg_num.
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unsigned Zeros = llvm::countr_zero(Imm);
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if (Zeros >= 8)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
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return MCDisassembler::Success;
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}
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#include "PPCGenDisassemblerTables.inc"
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DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &CS) const {
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auto *ReadFunc = IsLittleEndian ? support::endian::read32le
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: support::endian::read32be;
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// If this is an 8-byte prefixed instruction, handle it here.
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// Note: prefixed instructions aren't technically 8-byte entities - the prefix
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// appears in memory at an address 4 bytes prior to that of the base
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// instruction regardless of endianness. So we read the two pieces and
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// rebuild the 8-byte instruction.
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// TODO: In this function we call decodeInstruction several times with
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// different decoder tables. It may be possible to only call once by
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// looking at the top 6 bits of the instruction.
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if (STI.hasFeature(PPC::FeaturePrefixInstrs) && Bytes.size() >= 8) {
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uint32_t Prefix = ReadFunc(Bytes.data());
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uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
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uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
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DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
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this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 8;
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return result;
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}
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}
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// Get the four bytes of the instruction.
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Size = 4;
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if (Bytes.size() < 4) {
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Size = 0;
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return MCDisassembler::Fail;
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}
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// Read the instruction in the proper endianness.
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uint64_t Inst = ReadFunc(Bytes.data());
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if (STI.hasFeature(PPC::FeatureSPE)) {
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DecodeStatus result =
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decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
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if (result != MCDisassembler::Fail)
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return result;
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}
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return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
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}
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