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4b43ef3e5c
This is a follow-on to https://reviews.llvm.org/D134073. After https://reviews.llvm.org/D137653 we can now switch the PPC target away from positional operand matching. This patch fixes all of the "easy" cases. While this changes a large number of lines of tablegen source, it results in only a single non-comment change in the code generated by tablegen: the (unused) codegen-only "MTVRSAVEv" instruction was previously incorrectly encoding operand 0, and now encodes (correctly) operand 1. Changes which result in generated-code changes have been split off into the next (smaller) patch, for ease of review. Reviewed By: barannikov88 Differential Revision: https://reviews.llvm.org/D137661
89 lines
3.3 KiB
TableGen
89 lines
3.3 KiB
TableGen
//===-- PPCInstrFuture.td - Future Instruction Set --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the instructions introduced for the Future CPU.
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//
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//===----------------------------------------------------------------------===//
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class XOForm_RTAB5_L1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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string asmstr, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, NoItinerary> {
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bits<5> RT;
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bits<5> RA;
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bits<5> RB;
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bit L;
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let Pattern = pattern;
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bit RC = 0; // set by isRecordForm
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let Inst{6-10} = RT;
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let Inst{11-15} = RA;
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let Inst{16-20} = RB;
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let Inst{21} = L;
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let Inst{22-30} = xo;
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let Inst{31} = RC;
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}
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multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
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string asmbase, string asmstr,
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list<dag> pattern> {
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let BaseName = asmbase in {
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def NAME : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
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!strconcat(asmbase, !strconcat(" ", asmstr)),
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pattern>, RecFormRel;
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let Defs = [CR0] in
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def _rec : XOForm_RTAB5_L1<opcode, xo, OOL, IOL,
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!strconcat(asmbase, !strconcat(". ", asmstr)),
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[]>, isRecordForm, RecFormRel;
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}
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}
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let Predicates = [IsISAFuture] in {
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defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
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(ins g8rc:$RA, g8rc:$RB, u1imm:$L),
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"subfus", "$RT, $L, $RA, $RB", []>;
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}
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let Predicates = [HasVSX, IsISAFuture] in {
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let mayLoad = 1 in {
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def LXVRL : XX1Form_memOp<31, 525, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
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"lxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
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def LXVRLL : XX1Form_memOp<31, 557, (outs vsrc:$XT), (ins memr:$RA, g8rc:$RB),
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"lxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
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def LXVPRL : XForm_XTp5_XAB5<31, 589, (outs vsrprc:$XTp),
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(ins memr:$RA, g8rc:$RB),
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"lxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
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def LXVPRLL : XForm_XTp5_XAB5<31, 621, (outs vsrprc:$XTp),
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(ins memr:$RA, g8rc:$RB),
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"lxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
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}
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let mayStore = 1 in {
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def STXVRL : XX1Form_memOp<31, 653, (outs),
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(ins vsrc:$XT, memr:$RA, g8rc:$RB),
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"stxvrl $XT, $RA, $RB", IIC_LdStLoad, []>;
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def STXVRLL : XX1Form_memOp<31, 685, (outs),
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(ins vsrc:$XT, memr:$RA, g8rc:$RB),
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"stxvrll $XT, $RA, $RB", IIC_LdStLoad, []>;
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def STXVPRL : XForm_XTp5_XAB5<31, 717, (outs),
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(ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
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"stxvprl $XTp, $RA, $RB", IIC_LdStLFD, []>;
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def STXVPRLL : XForm_XTp5_XAB5<31, 749, (outs),
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(ins vsrprc:$XTp, memr:$RA, g8rc:$RB),
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"stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
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}
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}
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