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f6d431f208
Fixes #82659 There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI parameters, as shown in issue #82411. Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`, `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact. After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.
895 lines
31 KiB
C++
895 lines
31 KiB
C++
//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveVariable analysis pass. For each machine
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// instruction in the function, this pass calculates the set of registers that
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// are immediately dead after the instruction (i.e., the instruction calculates
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// the value, but it is never used) and the set of registers that are used by
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// the instruction, but are never used after the instruction (i.e., they are
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// killed).
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//
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// This class computes live variables using a sparse implementation based on
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// the machine code SSA form. This class computes live variable information for
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// each virtual and _register allocatable_ physical register in a function. It
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// uses the dominance properties of SSA form to efficiently compute live
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// variables for virtual registers, and assumes that physical registers are only
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// live within a single basic block (allowing it to do a single local analysis
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// to resolve physical register lifetimes in each basic block). If a physical
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// register is not register allocatable, it is not tracked. This is useful for
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// things like the stack pointer and condition codes.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/ADT/DenseSet.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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using namespace llvm;
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char LiveVariables::ID = 0;
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char &llvm::LiveVariablesID = LiveVariables::ID;
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INITIALIZE_PASS_BEGIN(LiveVariables, "livevars",
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"Live Variable Analysis", false, false)
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INITIALIZE_PASS_DEPENDENCY(UnreachableMachineBlockElim)
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INITIALIZE_PASS_END(LiveVariables, "livevars",
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"Live Variable Analysis", false, false)
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void LiveVariables::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequiredID(UnreachableMachineBlockElimID);
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineInstr *
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LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
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for (MachineInstr *MI : Kills)
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if (MI->getParent() == MBB)
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return MI;
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return nullptr;
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD void LiveVariables::VarInfo::dump() const {
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dbgs() << " Alive in blocks: ";
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for (unsigned AB : AliveBlocks)
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dbgs() << AB << ", ";
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dbgs() << "\n Killed by:";
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if (Kills.empty())
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dbgs() << " No instructions.\n";
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else {
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for (unsigned i = 0, e = Kills.size(); i != e; ++i)
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dbgs() << "\n #" << i << ": " << *Kills[i];
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dbgs() << "\n";
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}
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}
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#endif
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/// getVarInfo - Get (possibly creating) a VarInfo object for the given vreg.
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LiveVariables::VarInfo &LiveVariables::getVarInfo(Register Reg) {
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assert(Reg.isVirtual() && "getVarInfo: not a virtual register!");
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VirtRegInfo.grow(Reg);
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return VirtRegInfo[Reg];
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}
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void LiveVariables::MarkVirtRegAliveInBlock(
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VarInfo &VRInfo, MachineBasicBlock *DefBlock, MachineBasicBlock *MBB,
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SmallVectorImpl<MachineBasicBlock *> &WorkList) {
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unsigned BBNum = MBB->getNumber();
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// Check to see if this basic block is one of the killing blocks. If so,
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// remove it.
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for (unsigned i = 0, e = VRInfo.Kills.size(); i != e; ++i)
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if (VRInfo.Kills[i]->getParent() == MBB) {
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VRInfo.Kills.erase(VRInfo.Kills.begin()+i); // Erase entry
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break;
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}
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if (MBB == DefBlock) return; // Terminate recursion
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if (VRInfo.AliveBlocks.test(BBNum))
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return; // We already know the block is live
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// Mark the variable known alive in this bb
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VRInfo.AliveBlocks.set(BBNum);
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assert(MBB != &MF->front() && "Can't find reaching def for virtreg");
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WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
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}
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void LiveVariables::MarkVirtRegAliveInBlock(VarInfo &VRInfo,
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MachineBasicBlock *DefBlock,
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MachineBasicBlock *MBB) {
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SmallVector<MachineBasicBlock *, 16> WorkList;
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MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
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while (!WorkList.empty()) {
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MachineBasicBlock *Pred = WorkList.pop_back_val();
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MarkVirtRegAliveInBlock(VRInfo, DefBlock, Pred, WorkList);
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}
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}
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void LiveVariables::HandleVirtRegUse(Register Reg, MachineBasicBlock *MBB,
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MachineInstr &MI) {
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assert(MRI->getVRegDef(Reg) && "Register use before def!");
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unsigned BBNum = MBB->getNumber();
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VarInfo &VRInfo = getVarInfo(Reg);
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// Check to see if this basic block is already a kill block.
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if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
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// Yes, this register is killed in this basic block already. Increase the
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// live range by updating the kill instruction.
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VRInfo.Kills.back() = &MI;
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return;
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}
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#ifndef NDEBUG
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for (MachineInstr *Kill : VRInfo.Kills)
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assert(Kill->getParent() != MBB && "entry should be at end!");
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#endif
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// This situation can occur:
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//
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// ,------.
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// | |
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// | v
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// | t2 = phi ... t1 ...
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// | |
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// | v
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// | t1 = ...
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// | ... = ... t1 ...
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// | |
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// `------'
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//
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// where there is a use in a PHI node that's a predecessor to the defining
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// block. We don't want to mark all predecessors as having the value "alive"
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// in this case.
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if (MBB == MRI->getVRegDef(Reg)->getParent())
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return;
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// Add a new kill entry for this basic block. If this virtual register is
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// already marked as alive in this basic block, that means it is alive in at
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// least one of the successor blocks, it's not a kill.
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if (!VRInfo.AliveBlocks.test(BBNum))
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VRInfo.Kills.push_back(&MI);
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// Update all dominating blocks to mark them as "known live".
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for (MachineBasicBlock *Pred : MBB->predecessors())
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MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(Reg)->getParent(), Pred);
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}
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void LiveVariables::HandleVirtRegDef(Register Reg, MachineInstr &MI) {
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VarInfo &VRInfo = getVarInfo(Reg);
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if (VRInfo.AliveBlocks.empty())
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// If vr is not alive in any block, then defaults to dead.
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VRInfo.Kills.push_back(&MI);
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}
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/// FindLastPartialDef - Return the last partial def of the specified register.
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/// Also returns the sub-registers that're defined by the instruction.
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MachineInstr *
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LiveVariables::FindLastPartialDef(Register Reg,
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SmallSet<unsigned, 4> &PartDefRegs) {
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unsigned LastDefReg = 0;
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unsigned LastDefDist = 0;
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MachineInstr *LastDef = nullptr;
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for (MCPhysReg SubReg : TRI->subregs(Reg)) {
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MachineInstr *Def = PhysRegDef[SubReg];
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if (!Def)
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continue;
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unsigned Dist = DistanceMap[Def];
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if (Dist > LastDefDist) {
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LastDefReg = SubReg;
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LastDef = Def;
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LastDefDist = Dist;
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}
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}
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if (!LastDef)
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return nullptr;
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PartDefRegs.insert(LastDefReg);
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for (MachineOperand &MO : LastDef->all_defs()) {
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if (MO.getReg() == 0)
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continue;
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Register DefReg = MO.getReg();
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if (TRI->isSubRegister(Reg, DefReg)) {
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for (MCPhysReg SubReg : TRI->subregs_inclusive(DefReg))
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PartDefRegs.insert(SubReg);
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}
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}
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return LastDef;
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}
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/// HandlePhysRegUse - Turn previous partial def's into read/mod/writes. Add
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/// implicit defs to a machine instruction if there was an earlier def of its
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/// super-register.
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void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) {
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MachineInstr *LastDef = PhysRegDef[Reg];
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// If there was a previous use or a "full" def all is well.
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if (!LastDef && !PhysRegUse[Reg]) {
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// Otherwise, the last sub-register def implicitly defines this register.
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// e.g.
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// AH =
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// AL = ... implicit-def EAX, implicit killed AH
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// = AH
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// ...
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// = EAX
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// All of the sub-registers must have been defined before the use of Reg!
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SmallSet<unsigned, 4> PartDefRegs;
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MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs);
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// If LastPartialDef is NULL, it must be using a livein register.
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if (LastPartialDef) {
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LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
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true/*IsImp*/));
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PhysRegDef[Reg] = LastPartialDef;
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SmallSet<unsigned, 8> Processed;
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for (MCPhysReg SubReg : TRI->subregs(Reg)) {
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if (Processed.count(SubReg))
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continue;
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if (PartDefRegs.count(SubReg))
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continue;
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// This part of Reg was defined before the last partial def. It's killed
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// here.
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LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
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false/*IsDef*/,
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true/*IsImp*/));
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PhysRegDef[SubReg] = LastPartialDef;
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for (MCPhysReg SS : TRI->subregs(SubReg))
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Processed.insert(SS);
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}
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}
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} else if (LastDef && !PhysRegUse[Reg] &&
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!LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr))
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// Last def defines the super register, add an implicit def of reg.
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LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/,
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true/*IsImp*/));
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// Remember this use.
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for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
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PhysRegUse[SubReg] = &MI;
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}
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/// FindLastRefOrPartRef - Return the last reference or partial reference of
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/// the specified register.
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MachineInstr *LiveVariables::FindLastRefOrPartRef(Register Reg) {
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MachineInstr *LastDef = PhysRegDef[Reg];
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MachineInstr *LastUse = PhysRegUse[Reg];
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if (!LastDef && !LastUse)
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return nullptr;
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MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
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unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
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unsigned LastPartDefDist = 0;
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for (MCPhysReg SubReg : TRI->subregs(Reg)) {
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MachineInstr *Def = PhysRegDef[SubReg];
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if (Def && Def != LastDef) {
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// There was a def of this sub-register in between. This is a partial
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// def, keep track of the last one.
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unsigned Dist = DistanceMap[Def];
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if (Dist > LastPartDefDist)
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LastPartDefDist = Dist;
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} else if (MachineInstr *Use = PhysRegUse[SubReg]) {
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unsigned Dist = DistanceMap[Use];
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if (Dist > LastRefOrPartRefDist) {
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LastRefOrPartRefDist = Dist;
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LastRefOrPartRef = Use;
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}
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}
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}
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return LastRefOrPartRef;
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}
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bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) {
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MachineInstr *LastDef = PhysRegDef[Reg];
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MachineInstr *LastUse = PhysRegUse[Reg];
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if (!LastDef && !LastUse)
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return false;
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MachineInstr *LastRefOrPartRef = LastUse ? LastUse : LastDef;
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unsigned LastRefOrPartRefDist = DistanceMap[LastRefOrPartRef];
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// The whole register is used.
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// AL =
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// AH =
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//
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// = AX
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// = AL, implicit killed AX
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// AX =
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//
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// Or whole register is defined, but not used at all.
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// dead AX =
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// ...
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// AX =
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//
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// Or whole register is defined, but only partly used.
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// dead AX = implicit-def AL
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// = killed AL
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// AX =
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MachineInstr *LastPartDef = nullptr;
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unsigned LastPartDefDist = 0;
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SmallSet<unsigned, 8> PartUses;
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for (MCPhysReg SubReg : TRI->subregs(Reg)) {
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MachineInstr *Def = PhysRegDef[SubReg];
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if (Def && Def != LastDef) {
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// There was a def of this sub-register in between. This is a partial
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// def, keep track of the last one.
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unsigned Dist = DistanceMap[Def];
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if (Dist > LastPartDefDist) {
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LastPartDefDist = Dist;
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LastPartDef = Def;
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}
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continue;
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}
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if (MachineInstr *Use = PhysRegUse[SubReg]) {
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for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
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PartUses.insert(SS);
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unsigned Dist = DistanceMap[Use];
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if (Dist > LastRefOrPartRefDist) {
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LastRefOrPartRefDist = Dist;
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LastRefOrPartRef = Use;
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}
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}
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}
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if (!PhysRegUse[Reg]) {
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// Partial uses. Mark register def dead and add implicit def of
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// sub-registers which are used.
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// dead EAX = op implicit-def AL
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// That is, EAX def is dead but AL def extends pass it.
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PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true);
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for (MCPhysReg SubReg : TRI->subregs(Reg)) {
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if (!PartUses.count(SubReg))
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continue;
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bool NeedDef = true;
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if (PhysRegDef[Reg] == PhysRegDef[SubReg]) {
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MachineOperand *MO =
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PhysRegDef[Reg]->findRegisterDefOperand(SubReg, /*TRI=*/nullptr);
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if (MO) {
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NeedDef = false;
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assert(!MO->isDead());
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}
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}
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if (NeedDef)
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PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg,
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true/*IsDef*/, true/*IsImp*/));
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MachineInstr *LastSubRef = FindLastRefOrPartRef(SubReg);
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if (LastSubRef)
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LastSubRef->addRegisterKilled(SubReg, TRI, true);
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else {
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LastRefOrPartRef->addRegisterKilled(SubReg, TRI, true);
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for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
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PhysRegUse[SS] = LastRefOrPartRef;
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}
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for (MCPhysReg SS : TRI->subregs(SubReg))
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PartUses.erase(SS);
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}
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} else if (LastRefOrPartRef == PhysRegDef[Reg] && LastRefOrPartRef != MI) {
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if (LastPartDef)
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// The last partial def kills the register.
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LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/,
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true/*IsImp*/, true/*IsKill*/));
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else {
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MachineOperand *MO =
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LastRefOrPartRef->findRegisterDefOperand(Reg, TRI, false, false);
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bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
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// If the last reference is the last def, then it's not used at all.
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// That is, unless we are currently processing the last reference itself.
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LastRefOrPartRef->addRegisterDead(Reg, TRI, true);
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if (NeedEC) {
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// If we are adding a subreg def and the superreg def is marked early
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// clobber, add an early clobber marker to the subreg def.
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MO = LastRefOrPartRef->findRegisterDefOperand(Reg, /*TRI=*/nullptr);
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if (MO)
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MO->setIsEarlyClobber();
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}
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}
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} else
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LastRefOrPartRef->addRegisterKilled(Reg, TRI, true);
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return true;
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}
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void LiveVariables::HandleRegMask(const MachineOperand &MO, unsigned NumRegs) {
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// Call HandlePhysRegKill() for all live registers clobbered by Mask.
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// Clobbered registers are always dead, sp there is no need to use
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// HandlePhysRegDef().
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for (unsigned Reg = 1; Reg != NumRegs; ++Reg) {
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// Skip dead regs.
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if (!PhysRegDef[Reg] && !PhysRegUse[Reg])
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continue;
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// Skip mask-preserved regs.
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if (!MO.clobbersPhysReg(Reg))
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continue;
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// Kill the largest clobbered super-register.
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// This avoids needless implicit operands.
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unsigned Super = Reg;
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for (MCPhysReg SR : TRI->superregs(Reg))
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if (SR < NumRegs && (PhysRegDef[SR] || PhysRegUse[SR]) &&
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MO.clobbersPhysReg(SR))
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Super = SR;
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HandlePhysRegKill(Super, nullptr);
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}
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}
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void LiveVariables::HandlePhysRegDef(Register Reg, MachineInstr *MI,
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SmallVectorImpl<unsigned> &Defs) {
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// What parts of the register are previously defined?
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SmallSet<unsigned, 32> Live;
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if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
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for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg))
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Live.insert(SubReg);
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} else {
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for (MCPhysReg SubReg : TRI->subregs(Reg)) {
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// If a register isn't itself defined, but all parts that make up of it
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// are defined, then consider it also defined.
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// e.g.
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// AL =
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// AH =
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// = AX
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if (Live.count(SubReg))
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continue;
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if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) {
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for (MCPhysReg SS : TRI->subregs_inclusive(SubReg))
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Live.insert(SS);
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}
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}
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}
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// Start from the largest piece, find the last time any part of the register
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// is referenced.
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HandlePhysRegKill(Reg, MI);
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// Only some of the sub-registers are used.
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for (MCPhysReg SubReg : TRI->subregs(Reg)) {
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if (!Live.count(SubReg))
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// Skip if this sub-register isn't defined.
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continue;
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HandlePhysRegKill(SubReg, MI);
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}
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if (MI)
|
|
Defs.push_back(Reg); // Remember this def.
|
|
}
|
|
|
|
void LiveVariables::UpdatePhysRegDefs(MachineInstr &MI,
|
|
SmallVectorImpl<unsigned> &Defs) {
|
|
while (!Defs.empty()) {
|
|
Register Reg = Defs.pop_back_val();
|
|
for (MCPhysReg SubReg : TRI->subregs_inclusive(Reg)) {
|
|
PhysRegDef[SubReg] = &MI;
|
|
PhysRegUse[SubReg] = nullptr;
|
|
}
|
|
}
|
|
}
|
|
|
|
void LiveVariables::runOnInstr(MachineInstr &MI,
|
|
SmallVectorImpl<unsigned> &Defs,
|
|
unsigned NumRegs) {
|
|
assert(!MI.isDebugOrPseudoInstr());
|
|
// Process all of the operands of the instruction...
|
|
unsigned NumOperandsToProcess = MI.getNumOperands();
|
|
|
|
// Unless it is a PHI node. In this case, ONLY process the DEF, not any
|
|
// of the uses. They will be handled in other basic blocks.
|
|
if (MI.isPHI())
|
|
NumOperandsToProcess = 1;
|
|
|
|
// Clear kill and dead markers. LV will recompute them.
|
|
SmallVector<unsigned, 4> UseRegs;
|
|
SmallVector<unsigned, 4> DefRegs;
|
|
SmallVector<unsigned, 1> RegMasks;
|
|
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
|
|
MachineOperand &MO = MI.getOperand(i);
|
|
if (MO.isRegMask()) {
|
|
RegMasks.push_back(i);
|
|
continue;
|
|
}
|
|
if (!MO.isReg() || MO.getReg() == 0)
|
|
continue;
|
|
Register MOReg = MO.getReg();
|
|
if (MO.isUse()) {
|
|
if (!(MOReg.isPhysical() && MRI->isReserved(MOReg)))
|
|
MO.setIsKill(false);
|
|
if (MO.readsReg())
|
|
UseRegs.push_back(MOReg);
|
|
} else {
|
|
assert(MO.isDef());
|
|
// FIXME: We should not remove any dead flags. However the MIPS RDDSP
|
|
// instruction needs it at the moment: http://llvm.org/PR27116.
|
|
if (MOReg.isPhysical() && !MRI->isReserved(MOReg))
|
|
MO.setIsDead(false);
|
|
DefRegs.push_back(MOReg);
|
|
}
|
|
}
|
|
|
|
MachineBasicBlock *MBB = MI.getParent();
|
|
// Process all uses.
|
|
for (unsigned MOReg : UseRegs) {
|
|
if (Register::isVirtualRegister(MOReg))
|
|
HandleVirtRegUse(MOReg, MBB, MI);
|
|
else if (!MRI->isReserved(MOReg))
|
|
HandlePhysRegUse(MOReg, MI);
|
|
}
|
|
|
|
// Process all masked registers. (Call clobbers).
|
|
for (unsigned Mask : RegMasks)
|
|
HandleRegMask(MI.getOperand(Mask), NumRegs);
|
|
|
|
// Process all defs.
|
|
for (unsigned MOReg : DefRegs) {
|
|
if (Register::isVirtualRegister(MOReg))
|
|
HandleVirtRegDef(MOReg, MI);
|
|
else if (!MRI->isReserved(MOReg))
|
|
HandlePhysRegDef(MOReg, &MI, Defs);
|
|
}
|
|
UpdatePhysRegDefs(MI, Defs);
|
|
}
|
|
|
|
void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {
|
|
// Mark live-in registers as live-in.
|
|
SmallVector<unsigned, 4> Defs;
|
|
for (const auto &LI : MBB->liveins()) {
|
|
assert(Register::isPhysicalRegister(LI.PhysReg) &&
|
|
"Cannot have a live-in virtual register!");
|
|
HandlePhysRegDef(LI.PhysReg, nullptr, Defs);
|
|
}
|
|
|
|
// Loop over all of the instructions, processing them.
|
|
DistanceMap.clear();
|
|
unsigned Dist = 0;
|
|
for (MachineInstr &MI : *MBB) {
|
|
if (MI.isDebugOrPseudoInstr())
|
|
continue;
|
|
DistanceMap.insert(std::make_pair(&MI, Dist++));
|
|
|
|
runOnInstr(MI, Defs, NumRegs);
|
|
}
|
|
|
|
// Handle any virtual assignments from PHI nodes which might be at the
|
|
// bottom of this basic block. We check all of our successor blocks to see
|
|
// if they have PHI nodes, and if so, we simulate an assignment at the end
|
|
// of the current block.
|
|
if (!PHIVarInfo[MBB->getNumber()].empty()) {
|
|
SmallVectorImpl<unsigned> &VarInfoVec = PHIVarInfo[MBB->getNumber()];
|
|
|
|
for (unsigned I : VarInfoVec)
|
|
// Mark it alive only in the block we are representing.
|
|
MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getVRegDef(I)->getParent(),
|
|
MBB);
|
|
}
|
|
|
|
// MachineCSE may CSE instructions which write to non-allocatable physical
|
|
// registers across MBBs. Remember if any reserved register is liveout.
|
|
SmallSet<unsigned, 4> LiveOuts;
|
|
for (const MachineBasicBlock *SuccMBB : MBB->successors()) {
|
|
if (SuccMBB->isEHPad())
|
|
continue;
|
|
for (const auto &LI : SuccMBB->liveins()) {
|
|
if (!TRI->isInAllocatableClass(LI.PhysReg))
|
|
// Ignore other live-ins, e.g. those that are live into landing pads.
|
|
LiveOuts.insert(LI.PhysReg);
|
|
}
|
|
}
|
|
|
|
// Loop over PhysRegDef / PhysRegUse, killing any registers that are
|
|
// available at the end of the basic block.
|
|
for (unsigned i = 0; i != NumRegs; ++i)
|
|
if ((PhysRegDef[i] || PhysRegUse[i]) && !LiveOuts.count(i))
|
|
HandlePhysRegDef(i, nullptr, Defs);
|
|
}
|
|
|
|
bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
|
|
MF = &mf;
|
|
MRI = &mf.getRegInfo();
|
|
TRI = MF->getSubtarget().getRegisterInfo();
|
|
|
|
const unsigned NumRegs = TRI->getNumSupportedRegs(mf);
|
|
PhysRegDef.assign(NumRegs, nullptr);
|
|
PhysRegUse.assign(NumRegs, nullptr);
|
|
PHIVarInfo.resize(MF->getNumBlockIDs());
|
|
|
|
// FIXME: LiveIntervals will be updated to remove its dependence on
|
|
// LiveVariables to improve compilation time and eliminate bizarre pass
|
|
// dependencies. Until then, we can't change much in -O0.
|
|
if (!MRI->isSSA())
|
|
report_fatal_error("regalloc=... not currently supported with -O0");
|
|
|
|
analyzePHINodes(mf);
|
|
|
|
// Calculate live variable information in depth first order on the CFG of the
|
|
// function. This guarantees that we will see the definition of a virtual
|
|
// register before its uses due to dominance properties of SSA (except for PHI
|
|
// nodes, which are treated as a special case).
|
|
MachineBasicBlock *Entry = &MF->front();
|
|
df_iterator_default_set<MachineBasicBlock*,16> Visited;
|
|
|
|
for (MachineBasicBlock *MBB : depth_first_ext(Entry, Visited)) {
|
|
runOnBlock(MBB, NumRegs);
|
|
|
|
PhysRegDef.assign(NumRegs, nullptr);
|
|
PhysRegUse.assign(NumRegs, nullptr);
|
|
}
|
|
|
|
// Convert and transfer the dead / killed information we have gathered into
|
|
// VirtRegInfo onto MI's.
|
|
for (unsigned i = 0, e1 = VirtRegInfo.size(); i != e1; ++i) {
|
|
const Register Reg = Register::index2VirtReg(i);
|
|
for (unsigned j = 0, e2 = VirtRegInfo[Reg].Kills.size(); j != e2; ++j)
|
|
if (VirtRegInfo[Reg].Kills[j] == MRI->getVRegDef(Reg))
|
|
VirtRegInfo[Reg].Kills[j]->addRegisterDead(Reg, TRI);
|
|
else
|
|
VirtRegInfo[Reg].Kills[j]->addRegisterKilled(Reg, TRI);
|
|
}
|
|
|
|
// Check to make sure there are no unreachable blocks in the MC CFG for the
|
|
// function. If so, it is due to a bug in the instruction selector or some
|
|
// other part of the code generator if this happens.
|
|
#ifndef NDEBUG
|
|
for (const MachineBasicBlock &MBB : *MF)
|
|
assert(Visited.contains(&MBB) && "unreachable basic block found");
|
|
#endif
|
|
|
|
PhysRegDef.clear();
|
|
PhysRegUse.clear();
|
|
PHIVarInfo.clear();
|
|
|
|
return false;
|
|
}
|
|
|
|
void LiveVariables::recomputeForSingleDefVirtReg(Register Reg) {
|
|
assert(Reg.isVirtual());
|
|
|
|
VarInfo &VI = getVarInfo(Reg);
|
|
VI.AliveBlocks.clear();
|
|
VI.Kills.clear();
|
|
|
|
MachineInstr &DefMI = *MRI->getUniqueVRegDef(Reg);
|
|
MachineBasicBlock &DefBB = *DefMI.getParent();
|
|
|
|
// Initialize a worklist of BBs that Reg is live-to-end of. (Here
|
|
// "live-to-end" means Reg is live at the end of a block even if it is only
|
|
// live because of phi uses in a successor. This is different from isLiveOut()
|
|
// which does not consider phi uses.)
|
|
SmallVector<MachineBasicBlock *> LiveToEndBlocks;
|
|
SparseBitVector<> UseBlocks;
|
|
unsigned NumRealUses = 0;
|
|
for (auto &UseMO : MRI->use_nodbg_operands(Reg)) {
|
|
UseMO.setIsKill(false);
|
|
if (!UseMO.readsReg())
|
|
continue;
|
|
++NumRealUses;
|
|
MachineInstr &UseMI = *UseMO.getParent();
|
|
MachineBasicBlock &UseBB = *UseMI.getParent();
|
|
UseBlocks.set(UseBB.getNumber());
|
|
if (UseMI.isPHI()) {
|
|
// If Reg is used in a phi then it is live-to-end of the corresponding
|
|
// predecessor.
|
|
unsigned Idx = UseMO.getOperandNo();
|
|
LiveToEndBlocks.push_back(UseMI.getOperand(Idx + 1).getMBB());
|
|
} else if (&UseBB == &DefBB) {
|
|
// A non-phi use in the same BB as the single def must come after the def.
|
|
} else {
|
|
// Otherwise Reg must be live-to-end of all predecessors.
|
|
LiveToEndBlocks.append(UseBB.pred_begin(), UseBB.pred_end());
|
|
}
|
|
}
|
|
|
|
// Handle the case where all uses have been removed.
|
|
if (NumRealUses == 0) {
|
|
VI.Kills.push_back(&DefMI);
|
|
DefMI.addRegisterDead(Reg, nullptr);
|
|
return;
|
|
}
|
|
DefMI.clearRegisterDeads(Reg);
|
|
|
|
// Iterate over the worklist adding blocks to AliveBlocks.
|
|
bool LiveToEndOfDefBB = false;
|
|
while (!LiveToEndBlocks.empty()) {
|
|
MachineBasicBlock &BB = *LiveToEndBlocks.pop_back_val();
|
|
if (&BB == &DefBB) {
|
|
LiveToEndOfDefBB = true;
|
|
continue;
|
|
}
|
|
if (VI.AliveBlocks.test(BB.getNumber()))
|
|
continue;
|
|
VI.AliveBlocks.set(BB.getNumber());
|
|
LiveToEndBlocks.append(BB.pred_begin(), BB.pred_end());
|
|
}
|
|
|
|
// Recompute kill flags. For each block in which Reg is used but is not
|
|
// live-through, find the last instruction that uses Reg. Ignore phi nodes
|
|
// because they should not be included in Kills.
|
|
for (unsigned UseBBNum : UseBlocks) {
|
|
if (VI.AliveBlocks.test(UseBBNum))
|
|
continue;
|
|
MachineBasicBlock &UseBB = *MF->getBlockNumbered(UseBBNum);
|
|
if (&UseBB == &DefBB && LiveToEndOfDefBB)
|
|
continue;
|
|
for (auto &MI : reverse(UseBB)) {
|
|
if (MI.isDebugOrPseudoInstr())
|
|
continue;
|
|
if (MI.isPHI())
|
|
break;
|
|
if (MI.readsVirtualRegister(Reg)) {
|
|
assert(!MI.killsRegister(Reg, /*TRI=*/nullptr));
|
|
MI.addRegisterKilled(Reg, nullptr);
|
|
VI.Kills.push_back(&MI);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// replaceKillInstruction - Update register kill info by replacing a kill
|
|
/// instruction with a new one.
|
|
void LiveVariables::replaceKillInstruction(Register Reg, MachineInstr &OldMI,
|
|
MachineInstr &NewMI) {
|
|
VarInfo &VI = getVarInfo(Reg);
|
|
std::replace(VI.Kills.begin(), VI.Kills.end(), &OldMI, &NewMI);
|
|
}
|
|
|
|
/// removeVirtualRegistersKilled - Remove all killed info for the specified
|
|
/// instruction.
|
|
void LiveVariables::removeVirtualRegistersKilled(MachineInstr &MI) {
|
|
for (MachineOperand &MO : MI.operands()) {
|
|
if (MO.isReg() && MO.isKill()) {
|
|
MO.setIsKill(false);
|
|
Register Reg = MO.getReg();
|
|
if (Reg.isVirtual()) {
|
|
bool removed = getVarInfo(Reg).removeKill(MI);
|
|
assert(removed && "kill not in register's VarInfo?");
|
|
(void)removed;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// analyzePHINodes - Gather information about the PHI nodes in here. In
|
|
/// particular, we want to map the variable information of a virtual register
|
|
/// which is used in a PHI node. We map that to the BB the vreg is coming from.
|
|
///
|
|
void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
|
|
for (const auto &MBB : Fn)
|
|
for (const auto &BBI : MBB) {
|
|
if (!BBI.isPHI())
|
|
break;
|
|
for (unsigned i = 1, e = BBI.getNumOperands(); i != e; i += 2)
|
|
if (BBI.getOperand(i).readsReg())
|
|
PHIVarInfo[BBI.getOperand(i + 1).getMBB()->getNumber()]
|
|
.push_back(BBI.getOperand(i).getReg());
|
|
}
|
|
}
|
|
|
|
bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
|
|
Register Reg, MachineRegisterInfo &MRI) {
|
|
unsigned Num = MBB.getNumber();
|
|
|
|
// Reg is live-through.
|
|
if (AliveBlocks.test(Num))
|
|
return true;
|
|
|
|
// Registers defined in MBB cannot be live in.
|
|
const MachineInstr *Def = MRI.getVRegDef(Reg);
|
|
if (Def && Def->getParent() == &MBB)
|
|
return false;
|
|
|
|
// Reg was not defined in MBB, was it killed here?
|
|
return findKill(&MBB);
|
|
}
|
|
|
|
bool LiveVariables::isLiveOut(Register Reg, const MachineBasicBlock &MBB) {
|
|
LiveVariables::VarInfo &VI = getVarInfo(Reg);
|
|
|
|
SmallPtrSet<const MachineBasicBlock *, 8> Kills;
|
|
for (MachineInstr *MI : VI.Kills)
|
|
Kills.insert(MI->getParent());
|
|
|
|
// Loop over all of the successors of the basic block, checking to see if
|
|
// the value is either live in the block, or if it is killed in the block.
|
|
for (const MachineBasicBlock *SuccMBB : MBB.successors()) {
|
|
// Is it alive in this successor?
|
|
unsigned SuccIdx = SuccMBB->getNumber();
|
|
if (VI.AliveBlocks.test(SuccIdx))
|
|
return true;
|
|
// Or is it live because there is a use in a successor that kills it?
|
|
if (Kills.count(SuccMBB))
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
|
|
/// variables that are live out of DomBB will be marked as passing live through
|
|
/// BB.
|
|
void LiveVariables::addNewBlock(MachineBasicBlock *BB,
|
|
MachineBasicBlock *DomBB,
|
|
MachineBasicBlock *SuccBB) {
|
|
const unsigned NumNew = BB->getNumber();
|
|
|
|
DenseSet<unsigned> Defs, Kills;
|
|
|
|
MachineBasicBlock::iterator BBI = SuccBB->begin(), BBE = SuccBB->end();
|
|
for (; BBI != BBE && BBI->isPHI(); ++BBI) {
|
|
// Record the def of the PHI node.
|
|
Defs.insert(BBI->getOperand(0).getReg());
|
|
|
|
// All registers used by PHI nodes in SuccBB must be live through BB.
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
|
|
if (BBI->getOperand(i+1).getMBB() == BB)
|
|
getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
|
|
}
|
|
|
|
// Record all vreg defs and kills of all instructions in SuccBB.
|
|
for (; BBI != BBE; ++BBI) {
|
|
for (const MachineOperand &Op : BBI->operands()) {
|
|
if (Op.isReg() && Op.getReg().isVirtual()) {
|
|
if (Op.isDef())
|
|
Defs.insert(Op.getReg());
|
|
else if (Op.isKill())
|
|
Kills.insert(Op.getReg());
|
|
}
|
|
}
|
|
}
|
|
|
|
// Update info for all live variables
|
|
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
|
|
Register Reg = Register::index2VirtReg(i);
|
|
|
|
// If the Defs is defined in the successor it can't be live in BB.
|
|
if (Defs.count(Reg))
|
|
continue;
|
|
|
|
// If the register is either killed in or live through SuccBB it's also live
|
|
// through BB.
|
|
VarInfo &VI = getVarInfo(Reg);
|
|
if (Kills.count(Reg) || VI.AliveBlocks.test(SuccBB->getNumber()))
|
|
VI.AliveBlocks.set(NumNew);
|
|
}
|
|
}
|
|
|
|
/// addNewBlock - Add a new basic block BB as an empty succcessor to DomBB. All
|
|
/// variables that are live out of DomBB will be marked as passing live through
|
|
/// BB. LiveInSets[BB] is *not* updated (because it is not needed during
|
|
/// PHIElimination).
|
|
void LiveVariables::addNewBlock(MachineBasicBlock *BB,
|
|
MachineBasicBlock *DomBB,
|
|
MachineBasicBlock *SuccBB,
|
|
std::vector<SparseBitVector<>> &LiveInSets) {
|
|
const unsigned NumNew = BB->getNumber();
|
|
|
|
SparseBitVector<> &BV = LiveInSets[SuccBB->getNumber()];
|
|
for (unsigned R : BV) {
|
|
Register VirtReg = Register::index2VirtReg(R);
|
|
LiveVariables::VarInfo &VI = getVarInfo(VirtReg);
|
|
VI.AliveBlocks.set(NumNew);
|
|
}
|
|
// All registers used by PHI nodes in SuccBB must be live through BB.
|
|
for (MachineBasicBlock::iterator BBI = SuccBB->begin(),
|
|
BBE = SuccBB->end();
|
|
BBI != BBE && BBI->isPHI(); ++BBI) {
|
|
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
|
|
if (BBI->getOperand(i + 1).getMBB() == BB &&
|
|
BBI->getOperand(i).readsReg())
|
|
getVarInfo(BBI->getOperand(i).getReg())
|
|
.AliveBlocks.set(NumNew);
|
|
}
|
|
}
|