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The recently announced IBM z17 processor implements the architecture already supported as "arch15" in LLVM. This patch adds support for "z17" as an alternate architecture name for arch15. This patch also add the scheduler description for the z17 processor, provided by Jonas Paulsson.
70 lines
2.2 KiB
TableGen
70 lines
2.2 KiB
TableGen
//==-- SystemZSchedule.td - SystemZ Scheduling Definitions ----*- tblgen -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// Scheduler resources
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// These resources are used to express decoder grouping rules. The number of
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// decoder slots needed by an instructions is normally one, but there are
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// exceptions.
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def NormalGr : SchedWrite;
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def Cracked : SchedWrite;
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def GroupAlone : SchedWrite;
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def GroupAlone2 : SchedWrite;
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def GroupAlone3 : SchedWrite;
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def BeginGroup : SchedWrite;
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def EndGroup : SchedWrite;
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// A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
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def LSULatency : SchedWrite;
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// Operand WriteLatencies.
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foreach L = 1 - 30 in def "WLat"#L : SchedWrite;
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foreach L = 1 - 16 in
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def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
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LSULatency]>;
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// ReadAdvances, used for the register operand next to a memory operand,
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// modelling that the register operand is needed later than the address
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// operands.
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def RegReadAdv : SchedRead;
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foreach Num = ["", "2", "3", "4", "5", "6"] in {
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// Fixed-point units
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def "FXa"#Num : SchedWrite;
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def "FXb"#Num : SchedWrite;
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def "FXU"#Num : SchedWrite;
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// Load/store unit
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def "LSU"#Num : SchedWrite;
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// Vector sub units (z13 and later)
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def "VecBF"#Num : SchedWrite;
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def "VecDF"#Num : SchedWrite;
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def "VecDFX"#Num : SchedWrite;
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def "VecMul"#Num : SchedWrite;
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def "VecStr"#Num : SchedWrite;
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def "VecXsPm"#Num : SchedWrite;
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// Floating point unit (zEC12 and earlier)
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def "FPU"#Num : SchedWrite;
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def "DFU"#Num : SchedWrite;
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}
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def VecFPd : SchedWrite; // Blocking BFP div/sqrt unit (30 cycles).
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def VecFPd20 : SchedWrite; // Blocking BFP div/sqrt unit, 20 cycles.
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def VBU : SchedWrite; // Virtual branching unit
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def MCD : SchedWrite; // Millicode
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include "SystemZScheduleZ17.td"
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include "SystemZScheduleZ16.td"
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include "SystemZScheduleZ15.td"
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include "SystemZScheduleZ14.td"
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include "SystemZScheduleZ13.td"
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include "SystemZScheduleZEC12.td"
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include "SystemZScheduleZ196.td"
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