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80267f8148
The recently announced IBM z17 processor implements the architecture already supported as "arch15" in LLVM. This patch adds support for "z17" as an alternate architecture name for arch15. This patch also add the scheduler description for the z17 processor, provided by Jonas Paulsson.
163 lines
4.7 KiB
LLVM
163 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; Test 128-bit comparisons in vector registers on z17
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 -verify-machineinstrs | FileCheck %s
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; Equality comparison.
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define i64 @f1(i128 %value1, i128 %value2, i64 %a, i64 %b) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: vecq %v1, %v0
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; CHECK-NEXT: selgre %r2, %r4, %r5
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; CHECK-NEXT: br %r14
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%cond = icmp eq i128 %value1, %value2
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Inequality comparison.
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define i64 @f2(i128 %value1, i128 %value2, i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: vecq %v1, %v0
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; CHECK-NEXT: selgrlh %r2, %r4, %r5
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; CHECK-NEXT: br %r14
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%cond = icmp ne i128 %value1, %value2
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Signed greater-than comparison.
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define i64 @f3(i128 %value1, i128 %value2, i64 %a, i64 %b) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: vecq %v1, %v0
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; CHECK-NEXT: selgrh %r2, %r4, %r5
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; CHECK-NEXT: br %r14
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%cond = icmp sgt i128 %value1, %value2
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Signed less-than comparison.
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define i64 @f4(i128 %value1, i128 %value2, i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: vecq %v1, %v0
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; CHECK-NEXT: selgrl %r2, %r4, %r5
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; CHECK-NEXT: br %r14
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%cond = icmp slt i128 %value1, %value2
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Signed greater-or-equal comparison.
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define i64 @f5(i128 %value1, i128 %value2, i64 %a, i64 %b) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: vecq %v1, %v0
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; CHECK-NEXT: selgrhe %r2, %r4, %r5
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; CHECK-NEXT: br %r14
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%cond = icmp sge i128 %value1, %value2
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Signed less-or-equal comparison.
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define i64 @f6(i128 %value1, i128 %value2, i64 %a, i64 %b) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: vecq %v1, %v0
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; CHECK-NEXT: selgrle %r2, %r4, %r5
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; CHECK-NEXT: br %r14
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%cond = icmp sle i128 %value1, %value2
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Unsigned greater-than comparison.
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define i64 @f7(i128 %value1, i128 %value2, i64 %a, i64 %b) {
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; CHECK-LABEL: f7:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: veclq %v1, %v0
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; CHECK-NEXT: selgrh %r2, %r4, %r5
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; CHECK-NEXT: br %r14
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%cond = icmp ugt i128 %value1, %value2
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Unsigned less-than comparison.
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define i64 @f8(i128 %value1, i128 %value2, i64 %a, i64 %b) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: veclq %v1, %v0
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; CHECK-NEXT: selgrl %r2, %r4, %r5
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; CHECK-NEXT: br %r14
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%cond = icmp ult i128 %value1, %value2
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Unsigned greater-or-equal comparison.
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define i64 @f9(i128 %value1, i128 %value2, i64 %a, i64 %b) {
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; CHECK-LABEL: f9:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: veclq %v1, %v0
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; CHECK-NEXT: selgrhe %r2, %r4, %r5
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; CHECK-NEXT: br %r14
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%cond = icmp uge i128 %value1, %value2
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Unsigned less-or-equal comparison.
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define i64 @f10(i128 %value1, i128 %value2, i64 %a, i64 %b) {
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; CHECK-LABEL: f10:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: veclq %v1, %v0
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; CHECK-NEXT: selgrle %r2, %r4, %r5
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; CHECK-NEXT: br %r14
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%cond = icmp ule i128 %value1, %value2
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%res = select i1 %cond, i64 %a, i64 %b
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ret i64 %res
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}
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; Select between i128 values.
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define i128 @f11(i64 %value1, i64 %value2, i128 %a, i128 %b) {
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; CHECK-LABEL: f11:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r5), 3
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; CHECK-NEXT: cgrje %r3, %r4, .LBB10_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: vl %v1, 0(%r6), 3
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; CHECK-NEXT: vaq %v0, %v0, %v1
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; CHECK-NEXT: .LBB10_2:
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%cond = icmp eq i64 %value1, %value2
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%sum = add i128 %a, %b
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%res = select i1 %cond, i128 %a, i128 %sum
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ret i128 %res
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}
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