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80267f8148
The recently announced IBM z17 processor implements the architecture already supported as "arch15" in LLVM. This patch adds support for "z17" as an alternate architecture name for arch15. This patch also add the scheduler description for the z17 processor, provided by Jonas Paulsson.
57 lines
1.5 KiB
LLVM
57 lines
1.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; Test 128-bit division and remainder in vector registers on z17
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
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; Divide signed.
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define i128 @f1(i128 %a, i128 %b) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vdq %v0, %v1, %v0, 0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = sdiv i128 %a, %b
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ret i128 %res
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}
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; Divide unsigned.
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define i128 @f2(i128 %a, i128 %b) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vdlq %v0, %v1, %v0, 0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = udiv i128 %a, %b
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ret i128 %res
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}
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; Remainder signed.
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define i128 @f3(i128 %a, i128 %b) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vrq %v0, %v1, %v0, 0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = srem i128 %a, %b
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ret i128 %res
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}
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; Remainder unsigned.
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define i128 @f4(i128 %a, i128 %b) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vrlq %v0, %v1, %v0, 0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = urem i128 %a, %b
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ret i128 %res
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}
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