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80267f8148
The recently announced IBM z17 processor implements the architecture already supported as "arch15" in LLVM. This patch adds support for "z17" as an alternate architecture name for arch15. This patch also add the scheduler description for the z17 processor, provided by Jonas Paulsson.
542 lines
15 KiB
LLVM
542 lines
15 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; Test vector intrinsics added with z17.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
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declare <16 x i8> @llvm.s390.vgemb(<8 x i16>)
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declare <8 x i16> @llvm.s390.vgemh(<16 x i8>)
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declare <4 x i32> @llvm.s390.vgemf(<16 x i8>)
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declare <2 x i64> @llvm.s390.vgemg(<16 x i8>)
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declare i128 @llvm.s390.vgemq(<16 x i8>)
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declare i128 @llvm.s390.vuphg(<2 x i64>)
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declare i128 @llvm.s390.vuplhg(<2 x i64>)
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declare i128 @llvm.s390.vuplg(<2 x i64>)
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declare i128 @llvm.s390.vupllg(<2 x i64>)
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declare i128 @llvm.s390.vavgq(i128, i128)
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declare i128 @llvm.s390.vavglq(i128, i128)
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declare <16 x i8> @llvm.s390.veval(<16 x i8>, <16 x i8>, <16 x i8>, i32)
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declare <2 x i64> @llvm.s390.vmahg(<2 x i64>, <2 x i64>, <2 x i64>)
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declare i128 @llvm.s390.vmahq(i128, i128, i128)
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declare <2 x i64> @llvm.s390.vmalhg(<2 x i64>, <2 x i64>, <2 x i64>)
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declare i128 @llvm.s390.vmalhq(i128, i128, i128)
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declare i128 @llvm.s390.vmaeg(<2 x i64>, <2 x i64>, i128)
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declare i128 @llvm.s390.vmaleg(<2 x i64>, <2 x i64>, i128)
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declare i128 @llvm.s390.vmaog(<2 x i64>, <2 x i64>, i128)
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declare i128 @llvm.s390.vmalog(<2 x i64>, <2 x i64>, i128)
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declare <2 x i64> @llvm.s390.vmhg(<2 x i64>, <2 x i64>)
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declare i128 @llvm.s390.vmhq(i128, i128)
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declare <2 x i64> @llvm.s390.vmlhg(<2 x i64>, <2 x i64>)
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declare i128 @llvm.s390.vmlhq(i128, i128)
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declare i128 @llvm.s390.vmeg(<2 x i64>, <2 x i64>)
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declare i128 @llvm.s390.vmleg(<2 x i64>, <2 x i64>)
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declare i128 @llvm.s390.vmog(<2 x i64>, <2 x i64>)
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declare i128 @llvm.s390.vmlog(<2 x i64>, <2 x i64>)
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declare {i128, i32} @llvm.s390.vceqqs(i128, i128)
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declare {i128, i32} @llvm.s390.vchqs(i128, i128)
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declare {i128, i32} @llvm.s390.vchlqs(i128, i128)
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; VGEMB.
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define <16 x i8> @test_vgemb(<8 x i16> %a) {
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; CHECK-LABEL: test_vgemb:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgemb %v24, %v24
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; CHECK-NEXT: br %r14
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%res = call <16 x i8> @llvm.s390.vgemb(<8 x i16> %a)
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ret <16 x i8> %res
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}
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; VGEMH.
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define <8 x i16> @test_vgemh(<16 x i8> %a) {
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; CHECK-LABEL: test_vgemh:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgemh %v24, %v24
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; CHECK-NEXT: br %r14
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%res = call <8 x i16> @llvm.s390.vgemh(<16 x i8> %a)
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ret <8 x i16> %res
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}
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; VGEMF.
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define <4 x i32> @test_vgemf(<16 x i8> %a) {
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; CHECK-LABEL: test_vgemf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgemf %v24, %v24
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; CHECK-NEXT: br %r14
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%res = call <4 x i32> @llvm.s390.vgemf(<16 x i8> %a)
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ret <4 x i32> %res
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}
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; VGEMG.
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define <2 x i64> @test_vgemg(<16 x i8> %a) {
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; CHECK-LABEL: test_vgemg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgemg %v24, %v24
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; CHECK-NEXT: br %r14
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%res = call <2 x i64> @llvm.s390.vgemg(<16 x i8> %a)
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ret <2 x i64> %res
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}
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; VGEMQ.
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define i128 @test_vgemq(<16 x i8> %a) {
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; CHECK-LABEL: test_vgemq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vgemq %v0, %v24
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vgemq(<16 x i8> %a)
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ret i128 %res
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}
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; VUPHG.
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define i128 @test_vuphg(<2 x i64> %a) {
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; CHECK-LABEL: test_vuphg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vuphg %v0, %v24
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vuphg(<2 x i64> %a)
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ret i128 %res
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}
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; VUPLHG.
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define i128 @test_vuplhg(<2 x i64> %a) {
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; CHECK-LABEL: test_vuplhg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vuplhg %v0, %v24
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vuplhg(<2 x i64> %a)
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ret i128 %res
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}
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; VUPLG.
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define i128 @test_vuplg(<2 x i64> %a) {
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; CHECK-LABEL: test_vuplg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vuplg %v0, %v24
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vuplg(<2 x i64> %a)
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ret i128 %res
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}
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; VUPLLG.
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define i128 @test_vupllg(<2 x i64> %a) {
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; CHECK-LABEL: test_vupllg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vupllg %v0, %v24
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vupllg(<2 x i64> %a)
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ret i128 %res
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}
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; VAVGQ.
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define i128 @test_vavgq(i128 %a, i128 %b) {
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; CHECK-LABEL: test_vavgq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vavgq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vavgq(i128 %a, i128 %b)
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ret i128 %res
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}
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; VAVGLQ.
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define i128 @test_vavglq(i128 %a, i128 %b) {
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; CHECK-LABEL: test_vavglq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vavglq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vavglq(i128 %a, i128 %b)
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ret i128 %res
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}
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; VEVAL.
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define <16 x i8> @test_veval(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
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; CHECK-LABEL: test_veval:
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; CHECK: # %bb.0:
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; CHECK-NEXT: veval %v24, %v24, %v26, %v28, 123
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; CHECK-NEXT: br %r14
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%res = call <16 x i8> @llvm.s390.veval(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 123)
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ret <16 x i8> %res
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}
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; VMAHG.
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define <2 x i64> @test_vmahg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
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; CHECK-LABEL: test_vmahg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmahg %v24, %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%res = call <2 x i64> @llvm.s390.vmahg(<2 x i64> %a, <2 x i64> %b,
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<2 x i64> %c)
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ret <2 x i64> %res
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}
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; VMAHQ.
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define i128 @test_vmahq(i128 %a, i128 %b, i128 %c) {
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; CHECK-LABEL: test_vmahq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r5), 3
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vl %v2, 0(%r3), 3
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; CHECK-NEXT: vmahq %v0, %v2, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmahq(i128 %a, i128 %b, i128 %c)
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ret i128 %res
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}
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; VMALHG.
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define <2 x i64> @test_vmalhg(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
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; CHECK-LABEL: test_vmalhg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmalhg %v24, %v24, %v26, %v28
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; CHECK-NEXT: br %r14
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%res = call <2 x i64> @llvm.s390.vmalhg(<2 x i64> %a, <2 x i64> %b,
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<2 x i64> %c)
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ret <2 x i64> %res
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}
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; VMALHQ.
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define i128 @test_vmalhq(i128 %a, i128 %b, i128 %c) {
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; CHECK-LABEL: test_vmalhq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r5), 3
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; CHECK-NEXT: vl %v1, 0(%r4), 3
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; CHECK-NEXT: vl %v2, 0(%r3), 3
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; CHECK-NEXT: vmalhq %v0, %v2, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmalhq(i128 %a, i128 %b, i128 %c)
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ret i128 %res
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}
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; VMAEG.
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define i128 @test_vmaeg(<2 x i64> %a, <2 x i64> %b, i128 %c) {
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; CHECK-LABEL: test_vmaeg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vmaeg %v0, %v24, %v26, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmaeg(<2 x i64> %a, <2 x i64> %b, i128 %c)
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ret i128 %res
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}
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; VMALEG.
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define i128 @test_vmaleg(<2 x i64> %a, <2 x i64> %b, i128 %c) {
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; CHECK-LABEL: test_vmaleg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vmaleg %v0, %v24, %v26, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmaleg(<2 x i64> %a, <2 x i64> %b, i128 %c)
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ret i128 %res
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}
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; VMAOG.
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define i128 @test_vmaog(<2 x i64> %a, <2 x i64> %b, i128 %c) {
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; CHECK-LABEL: test_vmaog:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vmaog %v0, %v24, %v26, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmaog(<2 x i64> %a, <2 x i64> %b, i128 %c)
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ret i128 %res
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}
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; VMALOG.
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define i128 @test_vmalog(<2 x i64> %a, <2 x i64> %b, i128 %c) {
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; CHECK-LABEL: test_vmalog:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vmalog %v0, %v24, %v26, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmalog(<2 x i64> %a, <2 x i64> %b, i128 %c)
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ret i128 %res
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}
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; VMHG.
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define <2 x i64> @test_vmhg(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmhg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmhg %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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%res = call <2 x i64> @llvm.s390.vmhg(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %res
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}
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; VMHQ.
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define i128 @test_vmhq(i128 %a, i128 %b) {
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; CHECK-LABEL: test_vmhq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vmhq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmhq(i128 %a, i128 %b)
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ret i128 %res
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}
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; VMLHG.
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define <2 x i64> @test_vmlhg(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmlhg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmlhg %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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%res = call <2 x i64> @llvm.s390.vmlhg(<2 x i64> %a, <2 x i64> %b)
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ret <2 x i64> %res
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}
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; VMLHQ.
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define i128 @test_vmlhq(i128 %a, i128 %b) {
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; CHECK-LABEL: test_vmlhq:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r4), 3
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; CHECK-NEXT: vl %v1, 0(%r3), 3
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; CHECK-NEXT: vmlhq %v0, %v1, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmlhq(i128 %a, i128 %b)
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ret i128 %res
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}
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; VMEG.
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define i128 @test_vmeg(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmeg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmeg %v0, %v24, %v26
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmeg(<2 x i64> %a, <2 x i64> %b)
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ret i128 %res
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}
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; VMLEG.
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define i128 @test_vmleg(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmleg:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmleg %v0, %v24, %v26
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmleg(<2 x i64> %a, <2 x i64> %b)
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ret i128 %res
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}
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; VMOG.
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define i128 @test_vmog(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmog:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmog %v0, %v24, %v26
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmog(<2 x i64> %a, <2 x i64> %b)
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ret i128 %res
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}
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; VMLOG.
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define i128 @test_vmlog(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_vmlog:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmlog %v0, %v24, %v26
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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%res = call i128 @llvm.s390.vmlog(<2 x i64> %a, <2 x i64> %b)
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ret i128 %res
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}
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; VCEQGS with no processing of the result.
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define i32 @test_vceqqs(i128 %a, i128 %b) {
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; CHECK-LABEL: test_vceqqs:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vl %v0, 0(%r3), 3
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; CHECK-NEXT: vl %v1, 0(%r2), 3
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; CHECK-NEXT: vceqqs %v0, %v1, %v0
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; CHECK-NEXT: ipm %r2
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; CHECK-NEXT: srl %r2, 28
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; CHECK-NEXT: br %r14
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%call = call {i128, i32} @llvm.s390.vceqqs(i128 %a, i128 %b)
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%res = extractvalue {i128, i32} %call, 1
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ret i32 %res
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}
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; VCEQGS returning 1 if all elements are equal (CC == 0).
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define i32 @test_vceqqs_all_bool(i128 %a, i128 %b) {
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; CHECK-LABEL: test_vceqqs_all_bool:
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; CHECK: # %bb.0:
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|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vceqqs %v0, %v1, %v0
|
|
; CHECK-NEXT: lhi %r2, 0
|
|
; CHECK-NEXT: lochie %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
%call = call {i128, i32} @llvm.s390.vceqqs(i128 %a, i128 %b)
|
|
%res = extractvalue {i128, i32} %call, 1
|
|
%cmp = icmp ult i32 %res, 1
|
|
%ext = zext i1 %cmp to i32
|
|
ret i32 %ext
|
|
}
|
|
|
|
; VCEQGS, storing to %ptr if all elements are equal.
|
|
define i128 @test_vceqqs_all_store(i128 %a, i128 %b, ptr %ptr) {
|
|
; CHECK-LABEL: test_vceqqs_all_store:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r4), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r3), 3
|
|
; CHECK-NEXT: vceqqs %v0, %v1, %v0
|
|
; CHECK-NEXT: jnhe .LBB30_2
|
|
; CHECK-NEXT: # %bb.1: # %store
|
|
; CHECK-NEXT: mvhi 0(%r5), 0
|
|
; CHECK-NEXT: .LBB30_2: # %exit
|
|
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
|
; CHECK-NEXT: br %r14
|
|
%call = call {i128, i32} @llvm.s390.vceqqs(i128 %a, i128 %b)
|
|
%res = extractvalue {i128, i32} %call, 0
|
|
%cc = extractvalue {i128, i32} %call, 1
|
|
%cmp = icmp sle i32 %cc, 0
|
|
br i1 %cmp, label %store, label %exit
|
|
|
|
store:
|
|
store i32 0, ptr %ptr
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i128 %res
|
|
}
|
|
|
|
; VCHGS with no processing of the result.
|
|
define i32 @test_vchqs(i128 %a, i128 %b) {
|
|
; CHECK-LABEL: test_vchqs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vchqs %v0, %v1, %v0
|
|
; CHECK-NEXT: ipm %r2
|
|
; CHECK-NEXT: srl %r2, 28
|
|
; CHECK-NEXT: br %r14
|
|
%call = call {i128, i32} @llvm.s390.vchqs(i128 %a, i128 %b)
|
|
%res = extractvalue {i128, i32} %call, 1
|
|
ret i32 %res
|
|
}
|
|
|
|
; VCHGS returning 1 if all elements are higher (CC == 0).
|
|
define i32 @test_vchqs_all_bool(i128 %a, i128 %b) {
|
|
; CHECK-LABEL: test_vchqs_all_bool:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vchqs %v0, %v1, %v0
|
|
; CHECK-NEXT: lhi %r2, 0
|
|
; CHECK-NEXT: lochie %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
%call = call {i128, i32} @llvm.s390.vchqs(i128 %a, i128 %b)
|
|
%res = extractvalue {i128, i32} %call, 1
|
|
%cmp = icmp ult i32 %res, 1
|
|
%ext = zext i1 %cmp to i32
|
|
ret i32 %ext
|
|
}
|
|
|
|
; VCHGS, storing to %ptr if all elements are higher.
|
|
define i128 @test_vchqs_all_store(i128 %a, i128 %b, ptr %ptr) {
|
|
; CHECK-LABEL: test_vchqs_all_store:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r4), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r3), 3
|
|
; CHECK-NEXT: vchqs %v0, %v1, %v0
|
|
; CHECK-NEXT: jnhe .LBB33_2
|
|
; CHECK-NEXT: # %bb.1: # %store
|
|
; CHECK-NEXT: mvhi 0(%r5), 0
|
|
; CHECK-NEXT: .LBB33_2: # %exit
|
|
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
|
; CHECK-NEXT: br %r14
|
|
%call = call {i128, i32} @llvm.s390.vchqs(i128 %a, i128 %b)
|
|
%res = extractvalue {i128, i32} %call, 0
|
|
%cc = extractvalue {i128, i32} %call, 1
|
|
%cmp = icmp sle i32 %cc, 0
|
|
br i1 %cmp, label %store, label %exit
|
|
|
|
store:
|
|
store i32 0, ptr %ptr
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i128 %res
|
|
}
|
|
|
|
; VCHLQS with no processing of the result.
|
|
define i32 @test_vchlqs(i128 %a, i128 %b) {
|
|
; CHECK-LABEL: test_vchlqs:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vchlqs %v0, %v1, %v0
|
|
; CHECK-NEXT: ipm %r2
|
|
; CHECK-NEXT: srl %r2, 28
|
|
; CHECK-NEXT: br %r14
|
|
%call = call {i128, i32} @llvm.s390.vchlqs(i128 %a, i128 %b)
|
|
%res = extractvalue {i128, i32} %call, 1
|
|
ret i32 %res
|
|
}
|
|
|
|
; VCHLQS returning 1 if all elements are higher (CC == 0).
|
|
define i32 @test_vchlqs_all_bool(i128 %a, i128 %b) {
|
|
; CHECK-LABEL: test_vchlqs_all_bool:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r3), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r2), 3
|
|
; CHECK-NEXT: vchlqs %v0, %v1, %v0
|
|
; CHECK-NEXT: lhi %r2, 0
|
|
; CHECK-NEXT: lochie %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
%call = call {i128, i32} @llvm.s390.vchlqs(i128 %a, i128 %b)
|
|
%res = extractvalue {i128, i32} %call, 1
|
|
%cmp = icmp slt i32 %res, 1
|
|
%ext = zext i1 %cmp to i32
|
|
ret i32 %ext
|
|
}
|
|
|
|
; VCHLQS, storing to %ptr if all elements are higher.
|
|
define i128 @test_vchlqs_all_store(i128 %a, i128 %b, ptr %ptr) {
|
|
; CHECK-LABEL: test_vchlqs_all_store:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vl %v0, 0(%r4), 3
|
|
; CHECK-NEXT: vl %v1, 0(%r3), 3
|
|
; CHECK-NEXT: vchlqs %v0, %v1, %v0
|
|
; CHECK-NEXT: jnhe .LBB36_2
|
|
; CHECK-NEXT: # %bb.1: # %store
|
|
; CHECK-NEXT: mvhi 0(%r5), 0
|
|
; CHECK-NEXT: .LBB36_2: # %exit
|
|
; CHECK-NEXT: vst %v0, 0(%r2), 3
|
|
; CHECK-NEXT: br %r14
|
|
%call = call {i128, i32} @llvm.s390.vchlqs(i128 %a, i128 %b)
|
|
%res = extractvalue {i128, i32} %call, 0
|
|
%cc = extractvalue {i128, i32} %call, 1
|
|
%cmp = icmp ule i32 %cc, 0
|
|
br i1 %cmp, label %store, label %exit
|
|
|
|
store:
|
|
store i32 0, ptr %ptr
|
|
br label %exit
|
|
|
|
exit:
|
|
ret i128 %res
|
|
}
|
|
|