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The recently announced IBM z17 processor implements the architecture already supported as "arch15" in LLVM. This patch adds support for "z17" as an alternate architecture name for arch15. This patch also add the scheduler description for the z17 processor, provided by Jonas Paulsson.
33 lines
1.1 KiB
LLVM
33 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; Test high-part vector multiplication on z17
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z17 | FileCheck %s
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; Test a v2i64 unsigned high-part multiplication.
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define <2 x i64> @f1(<2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmlhg %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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%zext1 = zext <2 x i64> %val1 to <2 x i128>
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%zext2 = zext <2 x i64> %val2 to <2 x i128>
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%mulx = mul <2 x i128> %zext1, %zext2
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%highx = lshr <2 x i128> %mulx, splat(i128 64)
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%high = trunc <2 x i128> %highx to <2 x i64>
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ret <2 x i64> %high
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}
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; Test a v2i64 signed high-part multiplication.
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define <2 x i64> @f2(<2 x i64> %val1, <2 x i64> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmhg %v24, %v24, %v26
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; CHECK-NEXT: br %r14
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%sext1 = sext <2 x i64> %val1 to <2 x i128>
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%sext2 = sext <2 x i64> %val2 to <2 x i128>
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%mulx = mul <2 x i128> %sext1, %sext2
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%highx = lshr <2 x i128> %mulx, splat(i128 64)
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%high = trunc <2 x i128> %highx to <2 x i64>
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ret <2 x i64> %high
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}
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