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bb28442c0b
Previously, tail jump pseudo-opcodes were skipped by the `encodeInstruction()` call inside `X86AsmPrinter::LowerPATCHABLE_OP`. This caused emission of a 2-byte NOP and dropping of the tail jump. With this PR, we change `PATCHABLE_OP` to not wrap the first `MachineInstr` anymore, but inserting itself before, leaving the instruction unaltered. At lowering time in `X86AsmPrinter`, we now "look ahead" for the next non-pseudo `MachineInstr` and lower+encode it, to inspect its size. If the size is below what `PATCHABLE_OP` expects, it inserts NOPs; otherwise it does nothing. That way, now the first `MachineInstr` is always lowered as usual even if `"patchable-function"="prologue-short-redirect"` is used. Fixes https://github.com/llvm/llvm-project/issues/76879, https://github.com/llvm/llvm-project/issues/76958 and https://github.com/llvm/llvm-project/issues/59039
69 lines
2.6 KiB
C++
69 lines
2.6 KiB
C++
//===-- PatchableFunction.cpp - Patchable prologues for LLVM -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements edits function bodies in place to support the
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// "patchable-function" attribute.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/PassRegistry.h"
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using namespace llvm;
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namespace {
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struct PatchableFunction : public MachineFunctionPass {
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static char ID; // Pass identification, replacement for typeid
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PatchableFunction() : MachineFunctionPass(ID) {
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initializePatchableFunctionPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &F) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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};
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}
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bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) {
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MachineBasicBlock &FirstMBB = *MF.begin();
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if (MF.getFunction().hasFnAttribute("patchable-function-entry")) {
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const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
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// The initial .loc covers PATCHABLE_FUNCTION_ENTER.
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BuildMI(FirstMBB, FirstMBB.begin(), DebugLoc(),
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TII->get(TargetOpcode::PATCHABLE_FUNCTION_ENTER));
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return true;
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} else if (MF.getFunction().hasFnAttribute("patchable-function")) {
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#ifndef NDEBUG
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Attribute PatchAttr = MF.getFunction().getFnAttribute("patchable-function");
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StringRef PatchType = PatchAttr.getValueAsString();
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assert(PatchType == "prologue-short-redirect" && "Only possibility today!");
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#endif
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auto *TII = MF.getSubtarget().getInstrInfo();
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BuildMI(FirstMBB, FirstMBB.begin(), DebugLoc(),
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TII->get(TargetOpcode::PATCHABLE_OP))
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.addImm(2);
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MF.ensureAlignment(Align(16));
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return true;
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}
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return false;
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}
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char PatchableFunction::ID = 0;
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char &llvm::PatchableFunctionID = PatchableFunction::ID;
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INITIALIZE_PASS(PatchableFunction, "patchable-function",
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"Implement the 'patchable-function' attribute", false, false)
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