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850b492976
This adds an initial pac-ret gadget scanner to the llvm-bolt-binary-analysis-tool. The scanner is taken from the prototype that was published last year at https://github.com/llvm/llvm-project/compare/main...kbeyls:llvm-project:bolt-gadget-scanner-prototype, and has been discussed in RFC https://discourse.llvm.org/t/rfc-bolt-based-binary-analysis-tool-to-verify-correctness-of-security-hardening/78148 and in the EuroLLVM 2024 keynote "Does LLVM implement security hardenings correctly? A BOLT-based static analyzer to the rescue?" [Video](https://youtu.be/Sn_Fxa0tdpY) [Slides](https://llvm.org/devmtg/2024-04/slides/Keynote/Beyls_EuroLLVM2024_security_hardening_keynote.pdf) In the spirit of incremental development, this PR aims to add a minimal implementation that is "fully working" on its own, but has major limitations, as described in the bolt/docs/BinaryAnalysis.md documentation in this proposed commit. These and other limitations will be fixed in follow-on PRs, mostly based on code already existing in the prototype branch. I hope incrementally upstreaming will make it easier to review the code. Note that I believe that this could also form the basis of a scanner to analyze correct implementation of PAuthABI.
527 lines
20 KiB
C++
527 lines
20 KiB
C++
//===- bolt/Passes/NonPacProtectedRetAnalysis.cpp -------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a pass that looks for any AArch64 return instructions
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// that may not be protected by PAuth authentication instructions when needed.
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//
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//===----------------------------------------------------------------------===//
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#include "bolt/Passes/NonPacProtectedRetAnalysis.h"
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#include "bolt/Core/ParallelUtilities.h"
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#include "bolt/Passes/DataflowAnalysis.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/Format.h"
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#include <memory>
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#define DEBUG_TYPE "bolt-nonpacprotectedret"
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namespace llvm {
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namespace bolt {
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raw_ostream &operator<<(raw_ostream &OS, const MCInstInBBReference &Ref) {
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OS << "MCInstBBRef<";
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if (Ref.BB == nullptr)
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OS << "BB:(null)";
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else
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OS << "BB:" << Ref.BB->getName() << ":" << Ref.BBIndex;
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OS << ">";
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return OS;
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}
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raw_ostream &operator<<(raw_ostream &OS, const MCInstInBFReference &Ref) {
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OS << "MCInstBFRef<";
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if (Ref.BF == nullptr)
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OS << "BF:(null)";
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else
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OS << "BF:" << Ref.BF->getPrintName() << ":" << Ref.getOffset();
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OS << ">";
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return OS;
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}
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raw_ostream &operator<<(raw_ostream &OS, const MCInstReference &Ref) {
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switch (Ref.ParentKind) {
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case MCInstReference::BasicBlockParent:
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OS << Ref.U.BBRef;
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return OS;
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case MCInstReference::FunctionParent:
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OS << Ref.U.BFRef;
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return OS;
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}
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llvm_unreachable("");
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}
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namespace NonPacProtectedRetAnalysis {
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// The security property that is checked is:
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// When a register is used as the address to jump to in a return instruction,
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// that register must either:
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// (a) never be changed within this function, i.e. have the same value as when
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// the function started, or
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// (b) the last write to the register must be by an authentication instruction.
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// This property is checked by using dataflow analysis to keep track of which
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// registers have been written (def-ed), since last authenticated. Those are
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// exactly the registers containing values that should not be trusted (as they
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// could have changed since the last time they were authenticated). For pac-ret,
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// any return instruction using such a register is a gadget to be reported. For
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// PAuthABI, probably at least any indirect control flow using such a register
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// should be reported.
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// Furthermore, when producing a diagnostic for a found non-pac-ret protected
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// return, the analysis also lists the last instructions that wrote to the
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// register used in the return instruction.
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// The total set of registers used in return instructions in a given function is
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// small. It almost always is just `X30`.
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// In order to reduce the memory consumption of storing this additional state
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// during the dataflow analysis, this is computed by running the dataflow
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// analysis twice:
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// 1. In the first run, the dataflow analysis only keeps track of the security
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// property: i.e. which registers have been overwritten since the last
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// time they've been authenticated.
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// 2. If the first run finds any return instructions using a register last
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// written by a non-authenticating instruction, the dataflow analysis will
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// be run a second time. The first run will return which registers are used
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// in the gadgets to be reported. This information is used in the second run
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// to also track which instructions last wrote to those registers.
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struct State {
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/// A BitVector containing the registers that have been clobbered, and
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/// not authenticated.
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BitVector NonAutClobRegs;
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/// A vector of sets, only used in the second data flow run.
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/// Each element in the vector represents one of the registers for which we
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/// track the set of last instructions that wrote to this register. For
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/// pac-ret analysis, the expectation is that almost all return instructions
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/// only use register `X30`, and therefore, this vector will probably have
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/// length 1 in the second run.
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std::vector<SmallPtrSet<const MCInst *, 4>> LastInstWritingReg;
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State() {}
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State(unsigned NumRegs, unsigned NumRegsToTrack)
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: NonAutClobRegs(NumRegs), LastInstWritingReg(NumRegsToTrack) {}
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State &operator|=(const State &StateIn) {
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NonAutClobRegs |= StateIn.NonAutClobRegs;
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for (unsigned I = 0; I < LastInstWritingReg.size(); ++I)
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for (const MCInst *J : StateIn.LastInstWritingReg[I])
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LastInstWritingReg[I].insert(J);
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return *this;
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}
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bool operator==(const State &RHS) const {
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return NonAutClobRegs == RHS.NonAutClobRegs &&
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LastInstWritingReg == RHS.LastInstWritingReg;
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}
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bool operator!=(const State &RHS) const { return !((*this) == RHS); }
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};
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static void printLastInsts(
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raw_ostream &OS,
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const std::vector<SmallPtrSet<const MCInst *, 4>> &LastInstWritingReg) {
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OS << "Insts: ";
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for (unsigned I = 0; I < LastInstWritingReg.size(); ++I) {
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auto &Set = LastInstWritingReg[I];
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OS << "[" << I << "](";
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for (const MCInst *MCInstP : Set)
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OS << MCInstP << " ";
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OS << ")";
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}
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}
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raw_ostream &operator<<(raw_ostream &OS, const State &S) {
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OS << "pacret-state<";
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OS << "NonAutClobRegs: " << S.NonAutClobRegs << ", ";
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printLastInsts(OS, S.LastInstWritingReg);
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OS << ">";
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return OS;
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}
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class PacStatePrinter {
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public:
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void print(raw_ostream &OS, const State &State) const;
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explicit PacStatePrinter(const BinaryContext &BC) : BC(BC) {}
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private:
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const BinaryContext &BC;
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};
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void PacStatePrinter::print(raw_ostream &OS, const State &S) const {
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RegStatePrinter RegStatePrinter(BC);
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OS << "pacret-state<";
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OS << "NonAutClobRegs: ";
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RegStatePrinter.print(OS, S.NonAutClobRegs);
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OS << ", ";
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printLastInsts(OS, S.LastInstWritingReg);
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OS << ">";
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}
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class PacRetAnalysis
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: public DataflowAnalysis<PacRetAnalysis, State, /*Backward=*/false,
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PacStatePrinter> {
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using Parent =
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DataflowAnalysis<PacRetAnalysis, State, false, PacStatePrinter>;
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friend Parent;
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public:
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PacRetAnalysis(BinaryFunction &BF, MCPlusBuilder::AllocatorIdTy AllocId,
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const std::vector<MCPhysReg> &RegsToTrackInstsFor)
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: Parent(BF, AllocId), NumRegs(BF.getBinaryContext().MRI->getNumRegs()),
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RegsToTrackInstsFor(RegsToTrackInstsFor),
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TrackingLastInsts(!RegsToTrackInstsFor.empty()),
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Reg2StateIdx(RegsToTrackInstsFor.empty()
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? 0
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: *llvm::max_element(RegsToTrackInstsFor) + 1,
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-1) {
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for (unsigned I = 0; I < RegsToTrackInstsFor.size(); ++I)
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Reg2StateIdx[RegsToTrackInstsFor[I]] = I;
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}
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virtual ~PacRetAnalysis() {}
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protected:
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const unsigned NumRegs;
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/// RegToTrackInstsFor is the set of registers for which the dataflow analysis
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/// must compute which the last set of instructions writing to it are.
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const std::vector<MCPhysReg> RegsToTrackInstsFor;
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const bool TrackingLastInsts;
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/// Reg2StateIdx maps Register to the index in the vector used in State to
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/// track which instructions last wrote to this register.
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std::vector<uint16_t> Reg2StateIdx;
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SmallPtrSet<const MCInst *, 4> &lastWritingInsts(State &S,
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MCPhysReg Reg) const {
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assert(Reg < Reg2StateIdx.size());
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assert(isTrackingReg(Reg));
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return S.LastInstWritingReg[Reg2StateIdx[Reg]];
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}
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const SmallPtrSet<const MCInst *, 4> &lastWritingInsts(const State &S,
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MCPhysReg Reg) const {
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assert(Reg < Reg2StateIdx.size());
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assert(isTrackingReg(Reg));
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return S.LastInstWritingReg[Reg2StateIdx[Reg]];
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}
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bool isTrackingReg(MCPhysReg Reg) const {
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return llvm::is_contained(RegsToTrackInstsFor, Reg);
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}
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void preflight() {}
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State getStartingStateAtBB(const BinaryBasicBlock &BB) {
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return State(NumRegs, RegsToTrackInstsFor.size());
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}
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State getStartingStateAtPoint(const MCInst &Point) {
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return State(NumRegs, RegsToTrackInstsFor.size());
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}
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void doConfluence(State &StateOut, const State &StateIn) {
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PacStatePrinter P(BC);
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LLVM_DEBUG({
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dbgs() << " PacRetAnalysis::Confluence(\n";
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dbgs() << " State 1: ";
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P.print(dbgs(), StateOut);
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dbgs() << "\n";
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dbgs() << " State 2: ";
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P.print(dbgs(), StateIn);
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dbgs() << ")\n";
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});
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StateOut |= StateIn;
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LLVM_DEBUG({
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dbgs() << " merged state: ";
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P.print(dbgs(), StateOut);
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dbgs() << "\n";
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});
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}
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State computeNext(const MCInst &Point, const State &Cur) {
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PacStatePrinter P(BC);
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LLVM_DEBUG({
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dbgs() << " PacRetAnalysis::ComputeNext(";
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BC.InstPrinter->printInst(&const_cast<MCInst &>(Point), 0, "", *BC.STI,
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dbgs());
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dbgs() << ", ";
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P.print(dbgs(), Cur);
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dbgs() << ")\n";
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});
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State Next = Cur;
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BitVector Written = BitVector(NumRegs, false);
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// Assume a call can clobber all registers, including callee-saved
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// registers. There's a good chance that callee-saved registers will be
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// saved on the stack at some point during execution of the callee.
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// Therefore they should also be considered as potentially modified by an
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// attacker/written to.
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// Also, not all functions may respect the AAPCS ABI rules about
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// caller/callee-saved registers.
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if (BC.MIB->isCall(Point))
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Written.set();
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else
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// FIXME: `getWrittenRegs` only sets the register directly written in the
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// instruction, and the smaller aliasing registers. It does not set the
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// larger aliasing registers. To also set the larger aliasing registers,
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// we'd have to call `getClobberedRegs`.
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// It is unclear if there is any test case which shows a different
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// behaviour between using `getWrittenRegs` vs `getClobberedRegs`. We'd
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// first would like to see such a test case before making a decision
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// on whether using `getClobberedRegs` below would be better.
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// Also see the discussion on this at
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// https://github.com/llvm/llvm-project/pull/122304#discussion_r1939511909
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BC.MIB->getWrittenRegs(Point, Written);
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Next.NonAutClobRegs |= Written;
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// Keep track of this instruction if it writes to any of the registers we
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// need to track that for:
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for (MCPhysReg Reg : RegsToTrackInstsFor)
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if (Written[Reg])
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lastWritingInsts(Next, Reg) = {&Point};
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ErrorOr<MCPhysReg> AutReg = BC.MIB->getAuthenticatedReg(Point);
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if (AutReg && *AutReg != BC.MIB->getNoRegister()) {
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// FIXME: should we use `OnlySmaller=false` below? See similar
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// FIXME about `getWrittenRegs` above and further discussion about this
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// at
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// https://github.com/llvm/llvm-project/pull/122304#discussion_r1939515516
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Next.NonAutClobRegs.reset(
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BC.MIB->getAliases(*AutReg, /*OnlySmaller=*/true));
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if (TrackingLastInsts && isTrackingReg(*AutReg))
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lastWritingInsts(Next, *AutReg).clear();
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}
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LLVM_DEBUG({
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dbgs() << " .. result: (";
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P.print(dbgs(), Next);
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dbgs() << ")\n";
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});
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return Next;
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}
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StringRef getAnnotationName() const { return StringRef("PacRetAnalysis"); }
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public:
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std::vector<MCInstReference>
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getLastClobberingInsts(const MCInst Ret, BinaryFunction &BF,
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const BitVector &UsedDirtyRegs) const {
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if (!TrackingLastInsts)
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return {};
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auto MaybeState = getStateAt(Ret);
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if (!MaybeState)
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llvm_unreachable("Expected State to be present");
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const State &S = *MaybeState;
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// Due to aliasing registers, multiple registers may have been tracked.
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std::set<const MCInst *> LastWritingInsts;
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for (MCPhysReg TrackedReg : UsedDirtyRegs.set_bits()) {
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for (const MCInst *Inst : lastWritingInsts(S, TrackedReg))
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LastWritingInsts.insert(Inst);
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}
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std::vector<MCInstReference> Result;
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for (const MCInst *Inst : LastWritingInsts) {
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MCInstInBBReference Ref = MCInstInBBReference::get(Inst, BF);
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assert(Ref.BB != nullptr && "Expected Inst to be found");
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Result.push_back(MCInstReference(Ref));
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}
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return Result;
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}
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};
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FunctionAnalysisResult
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Analysis::computeDfState(PacRetAnalysis &PRA, BinaryFunction &BF,
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MCPlusBuilder::AllocatorIdTy AllocatorId) {
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PRA.run();
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LLVM_DEBUG({
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dbgs() << " After PacRetAnalysis:\n";
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BF.dump();
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});
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FunctionAnalysisResult Result;
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// Now scan the CFG for non-authenticating return instructions that use an
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// overwritten, non-authenticated register as return address.
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BinaryContext &BC = BF.getBinaryContext();
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for (BinaryBasicBlock &BB : BF) {
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for (int64_t I = BB.size() - 1; I >= 0; --I) {
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MCInst &Inst = BB.getInstructionAtIndex(I);
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if (BC.MIB->isReturn(Inst)) {
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ErrorOr<MCPhysReg> MaybeRetReg = BC.MIB->getRegUsedAsRetDest(Inst);
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if (MaybeRetReg.getError()) {
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Result.Diagnostics.push_back(std::make_shared<GenDiag>(
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MCInstInBBReference(&BB, I),
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"Warning: pac-ret analysis could not analyze this return "
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"instruction"));
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continue;
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}
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MCPhysReg RetReg = *MaybeRetReg;
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LLVM_DEBUG({
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dbgs() << " Found RET inst: ";
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BC.printInstruction(dbgs(), Inst);
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dbgs() << " RetReg: " << BC.MRI->getName(RetReg)
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<< "; authenticatesReg: "
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<< BC.MIB->isAuthenticationOfReg(Inst, RetReg) << "\n";
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});
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if (BC.MIB->isAuthenticationOfReg(Inst, RetReg))
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break;
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BitVector UsedDirtyRegs = PRA.getStateAt(Inst)->NonAutClobRegs;
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LLVM_DEBUG({
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dbgs() << " NonAutClobRegs at Ret: ";
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RegStatePrinter RSP(BC);
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RSP.print(dbgs(), UsedDirtyRegs);
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dbgs() << "\n";
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});
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UsedDirtyRegs &= BC.MIB->getAliases(RetReg, /*OnlySmaller=*/true);
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LLVM_DEBUG({
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dbgs() << " Intersection with RetReg: ";
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RegStatePrinter RSP(BC);
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RSP.print(dbgs(), UsedDirtyRegs);
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dbgs() << "\n";
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});
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if (UsedDirtyRegs.any()) {
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// This return instruction needs to be reported
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Result.Diagnostics.push_back(std::make_shared<Gadget>(
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MCInstInBBReference(&BB, I),
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PRA.getLastClobberingInsts(Inst, BF, UsedDirtyRegs)));
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for (MCPhysReg RetRegWithGadget : UsedDirtyRegs.set_bits())
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Result.RegistersAffected.insert(RetRegWithGadget);
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}
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}
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}
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}
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return Result;
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}
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void Analysis::runOnFunction(BinaryFunction &BF,
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MCPlusBuilder::AllocatorIdTy AllocatorId) {
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LLVM_DEBUG({
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dbgs() << "Analyzing in function " << BF.getPrintName() << ", AllocatorId "
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<< AllocatorId << "\n";
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BF.dump();
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});
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if (BF.hasCFG()) {
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PacRetAnalysis PRA(BF, AllocatorId, {});
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FunctionAnalysisResult FAR = computeDfState(PRA, BF, AllocatorId);
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if (!FAR.RegistersAffected.empty()) {
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// Redo the analysis, but now also track which instructions last wrote
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// to any of the registers in RetRegsWithGadgets, so that better
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// diagnostics can be produced.
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std::vector<MCPhysReg> RegsToTrack;
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for (MCPhysReg R : FAR.RegistersAffected)
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RegsToTrack.push_back(R);
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PacRetAnalysis PRWIA(BF, AllocatorId, RegsToTrack);
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FAR = computeDfState(PRWIA, BF, AllocatorId);
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}
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// `runOnFunction` is typically getting called from multiple threads in
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// parallel. Therefore, use a lock to avoid data races when storing the
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// result of the analysis in the `AnalysisResults` map.
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{
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std::lock_guard<std::mutex> Lock(AnalysisResultsMutex);
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AnalysisResults[&BF] = FAR;
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}
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}
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}
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static void printBB(const BinaryContext &BC, const BinaryBasicBlock *BB,
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size_t StartIndex = 0, size_t EndIndex = -1) {
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if (EndIndex == (size_t)-1)
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EndIndex = BB->size() - 1;
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const BinaryFunction *BF = BB->getFunction();
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for (unsigned I = StartIndex; I <= EndIndex; ++I) {
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// FIXME: this assumes all instructions are 4 bytes in size. This is true
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// for AArch64, but it might be good to extract this function so it can be
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// used elsewhere and for other targets too.
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uint64_t Address = BB->getOffset() + BF->getAddress() + 4 * I;
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const MCInst &Inst = BB->getInstructionAtIndex(I);
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if (BC.MIB->isCFI(Inst))
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continue;
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BC.printInstruction(outs(), Inst, Address, BF);
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}
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}
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static void reportFoundGadgetInSingleBBSingleOverwInst(
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raw_ostream &OS, const BinaryContext &BC, const MCInstReference OverwInst,
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const MCInstReference RetInst) {
|
|
BinaryBasicBlock *BB = RetInst.getBasicBlock();
|
|
assert(OverwInst.ParentKind == MCInstReference::BasicBlockParent);
|
|
assert(RetInst.ParentKind == MCInstReference::BasicBlockParent);
|
|
MCInstInBBReference OverwInstBB = OverwInst.U.BBRef;
|
|
if (BB == OverwInstBB.BB) {
|
|
// overwriting inst and ret instruction are in the same basic block.
|
|
assert(OverwInstBB.BBIndex < RetInst.U.BBRef.BBIndex);
|
|
OS << " This happens in the following basic block:\n";
|
|
printBB(BC, BB);
|
|
}
|
|
}
|
|
|
|
void Gadget::generateReport(raw_ostream &OS, const BinaryContext &BC) const {
|
|
GenDiag(RetInst, "non-protected ret found").generateReport(OS, BC);
|
|
|
|
BinaryFunction *BF = RetInst.getFunction();
|
|
OS << " The " << OverwritingRetRegInst.size()
|
|
<< " instructions that write to the return register after any "
|
|
"authentication are:\n";
|
|
// Sort by address to ensure output is deterministic.
|
|
std::vector<MCInstReference> ORRI = OverwritingRetRegInst;
|
|
llvm::sort(ORRI, [](const MCInstReference &A, const MCInstReference &B) {
|
|
return A.getAddress() < B.getAddress();
|
|
});
|
|
for (unsigned I = 0; I < ORRI.size(); ++I) {
|
|
MCInstReference InstRef = ORRI[I];
|
|
OS << " " << (I + 1) << ". ";
|
|
BC.printInstruction(OS, InstRef, InstRef.getAddress(), BF);
|
|
};
|
|
LLVM_DEBUG({
|
|
dbgs() << " .. OverWritingRetRegInst:\n";
|
|
for (MCInstReference Ref : OverwritingRetRegInst) {
|
|
dbgs() << " " << Ref << "\n";
|
|
}
|
|
});
|
|
if (OverwritingRetRegInst.size() == 1) {
|
|
const MCInstReference OverwInst = OverwritingRetRegInst[0];
|
|
assert(OverwInst.ParentKind == MCInstReference::BasicBlockParent);
|
|
reportFoundGadgetInSingleBBSingleOverwInst(OS, BC, OverwInst, RetInst);
|
|
}
|
|
}
|
|
|
|
void GenDiag::generateReport(raw_ostream &OS, const BinaryContext &BC) const {
|
|
BinaryFunction *BF = RetInst.getFunction();
|
|
BinaryBasicBlock *BB = RetInst.getBasicBlock();
|
|
|
|
OS << "\nGS-PACRET: " << Diag.Text;
|
|
OS << " in function " << BF->getPrintName();
|
|
if (BB)
|
|
OS << ", basic block " << BB->getName();
|
|
OS << ", at address " << llvm::format("%x", RetInst.getAddress()) << "\n";
|
|
OS << " The return instruction is ";
|
|
BC.printInstruction(OS, RetInst, RetInst.getAddress(), BF);
|
|
}
|
|
|
|
Error Analysis::runOnFunctions(BinaryContext &BC) {
|
|
ParallelUtilities::WorkFuncWithAllocTy WorkFun =
|
|
[&](BinaryFunction &BF, MCPlusBuilder::AllocatorIdTy AllocatorId) {
|
|
runOnFunction(BF, AllocatorId);
|
|
};
|
|
|
|
ParallelUtilities::PredicateTy SkipFunc = [&](const BinaryFunction &BF) {
|
|
return false;
|
|
};
|
|
|
|
ParallelUtilities::runOnEachFunctionWithUniqueAllocId(
|
|
BC, ParallelUtilities::SchedulingPolicy::SP_INST_LINEAR, WorkFun,
|
|
SkipFunc, "NonPacProtectedRetAnalysis");
|
|
|
|
for (BinaryFunction *BF : BC.getAllBinaryFunctions())
|
|
if (AnalysisResults.count(BF) > 0) {
|
|
for (const std::shared_ptr<Annotation> &A :
|
|
AnalysisResults[BF].Diagnostics)
|
|
A->generateReport(outs(), BC);
|
|
}
|
|
return Error::success();
|
|
}
|
|
|
|
} // namespace NonPacProtectedRetAnalysis
|
|
} // namespace bolt
|
|
} // namespace llvm
|