llvm-project/llvm/test/CodeGen/Mips/stack-alignment.ll
Simon Atanasyan 623282f0dd [mips] Explicitly select mips32r2 CPU for test cases require 64-bit FPU. NFC
Support for 64-bit coprocessors on a 32-bit architecture
was added in `MIPS32 R2`.

llvm-svn: 365507
2019-07-09 15:48:05 +00:00

20 lines
792 B
LLVM

; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
; RUN: llc -march=mipsel -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-32
; RUN: llc -march=mipsel -mattr=+fp64,+mips32r2 < %s | FileCheck %s -check-prefix=32
; RUN: llc -march=mips64el -mcpu=mips3 < %s | FileCheck %s -check-prefix=64
; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=64
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
; RUN: llc -march=mips64el -mcpu=mips64 -stack-alignment=32 < %s | FileCheck %s -check-prefix=A32-64
; 32: addiu $sp, $sp, -8
; 64: daddiu $sp, $sp, -16
; A32-32: addiu $sp, $sp, -32
; A32-64: daddiu $sp, $sp, -32
define i32 @foo1() #0 {
entry:
ret i32 14
}
attributes #0 = { "no-frame-pointer-elim"="true" }