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cc5a1b3dd9
MIR support is totally unusable for AMDGPU without this, since the set of reserved registers is set from fields here. Add a clone method to MachineFunctionInfo. This is a subtle variant of the copy constructor that is required if there are any MIR constructs that use pointers. Specifically, at minimum fields that reference MachineBasicBlocks or the MachineFunction need to be adjusted to the values in the new function.
38 lines
1.3 KiB
C++
38 lines
1.3 KiB
C++
//===-- X86MachineFunctionInfo.cpp - X86 machine function info ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "X86MachineFunctionInfo.h"
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#include "X86RegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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using namespace llvm;
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MachineFunctionInfo *X86MachineFunctionInfo::clone(
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BumpPtrAllocator &Allocator, MachineFunction &DestMF,
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const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
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const {
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return DestMF.cloneInfo<X86MachineFunctionInfo>(*this);
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}
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void X86MachineFunctionInfo::anchor() { }
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void X86MachineFunctionInfo::setRestoreBasePointer(const MachineFunction *MF) {
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if (!RestoreBasePointerOffset) {
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const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
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MF->getSubtarget().getRegisterInfo());
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unsigned SlotSize = RegInfo->getSlotSize();
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for (const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
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unsigned Reg = *CSR; ++CSR) {
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if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
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RestoreBasePointerOffset -= SlotSize;
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}
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}
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}
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