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91e9e31752
Currently the new PM infra for codegen puts everything into a MachineFunctionPassManager. The MachineFunctionPassManager owns both Module passes and MachineFunction passes, and batches adjacent MachineFunction passes like a typical PassManager. The current MachineFunctionAnalysisManager also directly references a module and function analysis manager to get results. The initial argument was that the codegen pipeline is relatively "flat", meaning it's mostly machine function passes with a couple of module passes here and there. However, there are a couple of issues with this as compared to a more structured nesting more like the optimization pipeline. For example, it doesn't allow running function passes then machine function passes on a function and its machine function all at once. It also currently requires the caller to split out the IR passes into one pass manager and the MIR passes into another pass manager. This patch rewrites the new pass manager infra for the codegen pipeline to be more similar to the nesting in the optimization pipeline. Basically, a Function contains a MachineFunction. So we can have Module -> Function -> MachineFunction adaptors. It also rewrites the analysis managers to have inner/outer proxies like the ones in the optimization pipeline. The new pass managers/adaptors/analysis managers can be seen in use in PassManagerTest.cpp. This allows us to consolidate to just having to add to one ModulePassManager when using the codegen pipeline. I haven't added the Function -> MachineFunction adaptor in this patch, but it should be added when we merge AddIRPass/AddMachinePass so that we can run IR and MIR passes on a function before proceeding to the next function. The MachineFunctionProperties infra for MIR verification is still WIP.
74 lines
2.6 KiB
C++
74 lines
2.6 KiB
C++
//===-- X86TargetMachine.h - Define TargetMachine for the X86 ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86TARGETMACHINE_H
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#define LLVM_LIB_TARGET_X86_X86TARGETMACHINE_H
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#include "X86Subtarget.h"
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#include "llvm/ADT/StringMap.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Target/TargetMachine.h"
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#include <memory>
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#include <optional>
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namespace llvm {
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class StringRef;
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class TargetTransformInfo;
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class X86TargetMachine final : public LLVMTargetMachine {
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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mutable StringMap<std::unique_ptr<X86Subtarget>> SubtargetMap;
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// True if this is used in JIT.
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bool IsJIT;
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public:
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X86TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
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bool JIT);
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~X86TargetMachine() override;
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const X86Subtarget *getSubtargetImpl(const Function &F) const override;
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// DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
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// subtargets are per-function entities based on the target-specific
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// attributes of each function.
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const X86Subtarget *getSubtargetImpl() const = delete;
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TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
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// Set up the pass pipeline.
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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MachineFunctionInfo *
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createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const override;
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Error buildCodeGenPipeline(ModulePassManager &, raw_pwrite_stream &,
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raw_pwrite_stream *, CodeGenFileType,
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CGPassBuilderOption,
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PassInstrumentationCallbacks *) override;
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bool isJIT() const { return IsJIT; }
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bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_X86_X86TARGETMACHINE_H
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