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cd269fee05
This both reapplies #118734, the initial attempt at this, and updates it significantly. First, it uses the newly added `StringTable` abstraction for string tables, and simplifies the construction to build the string table and info arrays separately. This should reduce any `constexpr` compile time memory or CPU cost of the original PR while significantly improving the APIs throughout. It also restructures the builtins to support sharding across several independent tables. This accomplishes two improvements from the original PR: 1) It improves the APIs used significantly. 2) When builtins are defined from different sources (like SVE vs MVE in AArch64), this allows each of them to build their own string table independently rather than having to merge the string tables and info structures. 3) It allows each shard to factor out a common prefix, often cutting the size of the strings needed for the builtins by a factor two. The second point is important both to allow different mechanisms of construction (for example a `.def` file and a tablegen'ed `.inc` file, or different tablegen'ed `.inc files), it also simply reduces the sizes of these tables which is valuable given how large they are in some cases. The third builds on that size reduction. Initially, we use this new sharding rather than merging tables in AArch64, LoongArch, RISCV, and X86. Mostly this helps ensure the system works, as without further changes these still push scaling limits. Subsequent commits will more deeply leverage the new structure, including using the prefix capabilities which cannot be easily factored out here and requires deep changes to the targets.
313 lines
7.3 KiB
C++
313 lines
7.3 KiB
C++
//===--- CSKY.cpp - Implement CSKY target feature support -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements CSKY TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "CSKY.h"
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using namespace clang;
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using namespace clang::targets;
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bool CSKYTargetInfo::isValidCPUName(StringRef Name) const {
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return llvm::CSKY::parseCPUArch(Name) != llvm::CSKY::ArchKind::INVALID;
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}
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bool CSKYTargetInfo::setCPU(const std::string &Name) {
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llvm::CSKY::ArchKind archKind = llvm::CSKY::parseCPUArch(Name);
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bool isValid = (archKind != llvm::CSKY::ArchKind::INVALID);
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if (isValid) {
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CPU = Name;
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Arch = archKind;
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}
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return isValid;
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}
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void CSKYTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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Builder.defineMacro("__csky__", "2");
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Builder.defineMacro("__CSKY__", "2");
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Builder.defineMacro("__ckcore__", "2");
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Builder.defineMacro("__CKCORE__", "2");
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Builder.defineMacro("__CSKYABI__", ABI == "abiv2" ? "2" : "1");
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Builder.defineMacro("__cskyabi__", ABI == "abiv2" ? "2" : "1");
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StringRef ArchName = "ck810";
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StringRef CPUName = "ck810";
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if (Arch != llvm::CSKY::ArchKind::INVALID) {
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ArchName = llvm::CSKY::getArchName(Arch);
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CPUName = CPU;
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}
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Builder.defineMacro("__" + ArchName.upper() + "__");
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Builder.defineMacro("__" + ArchName.lower() + "__");
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if (ArchName != CPUName) {
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Builder.defineMacro("__" + CPUName.upper() + "__");
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Builder.defineMacro("__" + CPUName.lower() + "__");
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}
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// TODO: Add support for BE if BE was supported later
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StringRef endian = "__cskyLE__";
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Builder.defineMacro(endian);
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Builder.defineMacro(endian.upper());
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Builder.defineMacro(endian.lower());
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if (DSPV2) {
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StringRef dspv2 = "__CSKY_DSPV2__";
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Builder.defineMacro(dspv2);
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Builder.defineMacro(dspv2.lower());
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}
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if (VDSPV2) {
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StringRef vdspv2 = "__CSKY_VDSPV2__";
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Builder.defineMacro(vdspv2);
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Builder.defineMacro(vdspv2.lower());
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if (HardFloat) {
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StringRef vdspv2_f = "__CSKY_VDSPV2_F__";
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Builder.defineMacro(vdspv2_f);
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Builder.defineMacro(vdspv2_f.lower());
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}
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}
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if (VDSPV1) {
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StringRef vdspv1_64 = "__CSKY_VDSP64__";
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StringRef vdspv1_128 = "__CSKY_VDSP128__";
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Builder.defineMacro(vdspv1_64);
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Builder.defineMacro(vdspv1_64.lower());
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Builder.defineMacro(vdspv1_128);
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Builder.defineMacro(vdspv1_128.lower());
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}
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if (is3E3R1) {
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StringRef is3e3r1 = "__CSKY_3E3R1__";
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Builder.defineMacro(is3e3r1);
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Builder.defineMacro(is3e3r1.lower());
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}
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}
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bool CSKYTargetInfo::hasFeature(StringRef Feature) const {
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return llvm::StringSwitch<bool>(Feature)
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.Case("hard-float", HardFloat)
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.Case("hard-float-abi", HardFloatABI)
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.Case("fpuv2_sf", FPUV2_SF)
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.Case("fpuv2_df", FPUV2_DF)
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.Case("fpuv3_sf", FPUV3_SF)
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.Case("fpuv3_df", FPUV3_DF)
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.Case("vdspv2", VDSPV2)
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.Case("dspv2", DSPV2)
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.Case("vdspv1", VDSPV1)
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.Case("3e3r1", is3E3R1)
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.Default(false);
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}
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bool CSKYTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) {
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for (const auto &Feature : Features) {
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if (Feature == "+hard-float")
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HardFloat = true;
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if (Feature == "+hard-float-abi")
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HardFloatABI = true;
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if (Feature == "+fpuv2_sf")
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FPUV2_SF = true;
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if (Feature == "+fpuv2_df")
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FPUV2_DF = true;
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if (Feature == "+fpuv3_sf")
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FPUV3_SF = true;
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if (Feature == "+fpuv3_df")
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FPUV3_DF = true;
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if (Feature == "+vdspv2")
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VDSPV2 = true;
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if (Feature == "+dspv2")
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DSPV2 = true;
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if (Feature == "+vdspv1")
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VDSPV1 = true;
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if (Feature == "+3e3r1")
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is3E3R1 = true;
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}
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return true;
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}
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ArrayRef<const char *> CSKYTargetInfo::getGCCRegNames() const {
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static const char *const GCCRegNames[] = {
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// Integer registers
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"r0",
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"r1",
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"r2",
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"r3",
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"r4",
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"r5",
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"r6",
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"r7",
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"r8",
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"r9",
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"r10",
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"r11",
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"r12",
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"r13",
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"r14",
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"r15",
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"r16",
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"r17",
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"r18",
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"r19",
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"r20",
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"r21",
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"r22",
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"r23",
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"r24",
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"r25",
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"r26",
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"r27",
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"r28",
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"r29",
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"r30",
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"r31",
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// Floating point registers
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"fr0",
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"fr1",
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"fr2",
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"fr3",
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"fr4",
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"fr5",
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"fr6",
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"fr7",
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"fr8",
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"fr9",
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"fr10",
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"fr11",
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"fr12",
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"fr13",
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"fr14",
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"fr15",
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"fr16",
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"fr17",
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"fr18",
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"fr19",
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"fr20",
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"fr21",
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"fr22",
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"fr23",
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"fr24",
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"fr25",
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"fr26",
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"fr27",
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"fr28",
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"fr29",
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"fr30",
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"fr31",
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};
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return llvm::ArrayRef(GCCRegNames);
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}
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ArrayRef<TargetInfo::GCCRegAlias> CSKYTargetInfo::getGCCRegAliases() const {
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static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
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{{"a0"}, "r0"},
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{{"a1"}, "r1"},
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{{"a2"}, "r2"},
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{{"a3"}, "r3"},
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{{"l0"}, "r4"},
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{{"l1"}, "r5"},
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{{"l2"}, "r6"},
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{{"l3"}, "r7"},
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{{"l4"}, "r8"},
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{{"l5"}, "r9"},
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{{"l6"}, "r10"},
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{{"l7"}, "r11"},
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{{"t0"}, "r12"},
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{{"t1"}, "r13"},
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{{"sp"}, "r14"},
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{{"lr"}, "r15"},
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{{"l8"}, "r16"},
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{{"l9"}, "r17"},
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{{"t2"}, "r18"},
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{{"t3"}, "r19"},
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{{"t4"}, "r20"},
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{{"t5"}, "r21"},
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{{"t6"}, "r22"},
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{{"t7", "fp"}, "r23"},
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{{"t8", "top"}, "r24"},
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{{"t9", "bsp"}, "r25"},
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{{"r26"}, "r26"},
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{{"r27"}, "r27"},
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{{"gb", "rgb", "rdb"}, "r28"},
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{{"tb", "rtb"}, "r29"},
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{{"svbr"}, "r30"},
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{{"tls"}, "r31"},
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{{"vr0"}, "fr0"},
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{{"vr1"}, "fr1"},
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{{"vr2"}, "fr2"},
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{{"vr3"}, "fr3"},
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{{"vr4"}, "fr4"},
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{{"vr5"}, "fr5"},
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{{"vr6"}, "fr6"},
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{{"vr7"}, "fr7"},
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{{"vr8"}, "fr8"},
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{{"vr9"}, "fr9"},
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{{"vr10"}, "fr10"},
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{{"vr11"}, "fr11"},
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{{"vr12"}, "fr12"},
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{{"vr13"}, "fr13"},
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{{"vr14"}, "fr14"},
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{{"vr15"}, "fr15"},
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{{"vr16"}, "fr16"},
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{{"vr17"}, "fr17"},
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{{"vr18"}, "fr18"},
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{{"vr19"}, "fr19"},
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{{"vr20"}, "fr20"},
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{{"vr21"}, "fr21"},
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{{"vr22"}, "fr22"},
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{{"vr23"}, "fr23"},
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{{"vr24"}, "fr24"},
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{{"vr25"}, "fr25"},
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{{"vr26"}, "fr26"},
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{{"vr27"}, "fr27"},
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{{"vr28"}, "fr28"},
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{{"vr29"}, "fr29"},
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{{"vr30"}, "fr30"},
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{{"vr31"}, "fr31"},
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};
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return llvm::ArrayRef(GCCRegAliases);
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}
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bool CSKYTargetInfo::validateAsmConstraint(
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const char *&Name, TargetInfo::ConstraintInfo &Info) const {
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switch (*Name) {
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default:
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return false;
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case 'a':
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case 'b':
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case 'c':
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case 'y':
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case 'l':
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case 'h':
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case 'w':
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case 'v': // A floating-point and vector register.
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case 'z':
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Info.setAllowsRegister();
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return true;
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}
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}
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unsigned CSKYTargetInfo::getMinGlobalAlign(uint64_t Size,
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bool HasNonWeakDef) const {
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if (Size >= 32)
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return 32;
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return 0;
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}
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