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39dac1f7f6
Implement target builtins for gfx90a including fadd64, fadd32, add2h, max and min on various global, flat and ds address spaces for which intrinsics are implemented. Differential Revision: https://reviews.llvm.org/D106909
15 lines
611 B
Common Lisp
15 lines
611 B
Common Lisp
// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -O0 -cl-std=CL2.0 -triple amdgcn-amd-amdhsa -target-cpu gfx1030 \
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// RUN: -S -o - %s
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// RUN: %clang_cc1 -O0 -cl-std=CL2.0 -triple amdgcn-amd-amdhsa -target-cpu gfx1030 \
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// RUN: -S -o - %s | FileCheck -check-prefix=GFX1030 %s
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// CHECK-LABEL: test_ds_addf_local
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// CHECK: call float @llvm.amdgcn.ds.fadd.f32(float addrspace(3)* %{{.*}}, float %{{.*}},
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// GFX1030-LABEL: test_ds_addf_local$local
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// GFX1030: ds_add_rtn_f32
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void test_ds_addf_local(__local float *addr, float x){
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float *rtn;
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*rtn = __builtin_amdgcn_ds_atomic_fadd_f32(addr, x);
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}
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