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This change seeks to add support for vendor flavoured SPIRV - more specifically, AMDGCN flavoured SPIRV. The aim is to generate SPIRV that carries some extra bits of information that are only usable by AMDGCN targets, forfeiting absolute genericity to obtain greater expressiveness for target features: - AMDGCN inline ASM is allowed/supported, under the assumption that the [SPV_INTEL_inline_assembly](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_inline_assembly.asciidoc) extension is enabled/used - AMDGCN target specific builtins are allowed/supported, under the assumption that e.g. the `--spirv-allow-unknown-intrinsics` option is enabled when using the downstream translator - the featureset matches the union of AMDGCN targets' features - the datalayout string is overspecified to affix both the program address space and the alloca address space, the latter under the assumption that the [SPV_INTEL_function_pointers](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_function_pointers.asciidoc) extension is enabled/used, case in which the extant SPIRV datalayout string would lead to pointers to function pointing to the private address space, which would be wrong. Existing AMDGCN tests are extended to cover this new target. It is currently dormant / will require some additional changes, but I thought I'd rather put it up for review to get feedback as early as possible. I will note that an alternative option is to place this under AMDGPU, but that seems slightly less natural, since this is still SPIRV, albeit relaxed in terms of preconditions & constrained in terms of postconditions, and only guaranteed to be usable on AMDGCN targets (it is still possible to obtain pristine portable SPIRV through usage of the flavoured target, though).
51 lines
2.2 KiB
Common Lisp
51 lines
2.2 KiB
Common Lisp
// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -emit-llvm -O0 -o - -triple amdgcn %s | FileCheck %s
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// RUN: %clang_cc1 -emit-llvm -O0 -o - -triple spirv64-amd-amdhsa %s | FileCheck %s
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typedef float float32 __attribute__((ext_vector_type(32)));
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kernel void test_long(int arg0) {
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long v15_16;
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// CHECK: call{{.*}} i64 asm sideeffect "v_lshlrev_b64 v[15:16], 0, $0", "={v[15:16]},v"
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__asm volatile("v_lshlrev_b64 v[15:16], 0, %0" : "={v[15:16]}"(v15_16) : "v"(arg0));
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}
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kernel void test_agpr() {
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float32 acc_c;
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float reg_a;
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float reg_b;
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float32 reg_c;
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// CHECK: call{{.*}} <32 x float> asm "v_mfma_f32_32x32x1f32 $0, $1, $2, $3", "=a,v,v,a,~{a0},~{a1},~{a2},~{a3},~{a4},~{a5},~{a6},~{a7},~{a8},~{a9},~{a10},~{a11},~{a12},~{a13},~{a14},~{a15},~{a16},~{a17},~{a18},~{a19},~{a20},~{a21},~{a22},~{a23},~{a24},~{a25},~{a26},~{a27},~{a28},~{a29},~{a30},~{a31}"
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__asm ("v_mfma_f32_32x32x1f32 %0, %1, %2, %3"
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: "=a"(acc_c)
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: "v"(reg_a), "v"(reg_b), "a"(reg_c)
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: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
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"a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15",
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"a16", "a17", "a18", "a19", "a20", "a21", "a22", "a23",
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"a24", "a25", "a26", "a27", "a28", "a29", "a30", "a31");
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// CHECK: call{{.*}} <32 x float> asm sideeffect "v_mfma_f32_32x32x1f32 a[0:31], $0, $1, a[0:31]", "={a[0:31]},v,v,{a[0:31]}"
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__asm volatile("v_mfma_f32_32x32x1f32 a[0:31], %0, %1, a[0:31]"
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: "={a[0:31]}"(acc_c)
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: "v"(reg_a),"v"(reg_b), "{a[0:31]}"(reg_c));
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// CHECK: call{{.*}} float asm "v_accvgpr_read_b32 $0, $1", "={a1},{a1}"
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__asm ("v_accvgpr_read_b32 %0, %1"
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: "={a1}"(reg_a)
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: "{a1}"(reg_b));
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}
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kernel void test_constraint_DA() {
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const long x = 0x200000001;
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int res;
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// CHECK: call{{.*}} i32 asm sideeffect "v_mov_b32 $0, $1 & 0xFFFFFFFF", "=v,^DA"(i64 8589934593)
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__asm volatile("v_mov_b32 %0, %1 & 0xFFFFFFFF" : "=v"(res) : "DA"(x));
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}
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kernel void test_constraint_DB() {
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const long x = 0x200000001;
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int res;
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// CHECK: call{{.*}} i32 asm sideeffect "v_mov_b32 $0, $1 & 0xFFFFFFFF", "=v,^DB"(i64 8589934593)
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__asm volatile("v_mov_b32 %0, %1 & 0xFFFFFFFF" : "=v"(res) : "DB"(x));
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}
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