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This is the clang commit associated with llvm r248887. This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234], vst[234]lane ARM neon intrinsics and associates an address space with the pointer that these intrinsics take. This changes, e.g., <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) to <2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32) This change ensures that address spaces are fully taken into account in the ARM target during lowering of interleaved loads and stores. Differential Revision: http://reviews.llvm.org/D13127 llvm-svn: 248888
31 lines
1.0 KiB
C
31 lines
1.0 KiB
C
// REQUIRES: arm-registered-target
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// RUN: %clang_cc1 -triple thumbv7-apple-darwin \
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// RUN: -target-abi apcs-gnu \
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// RUN: -target-cpu cortex-a8 \
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// RUN: -mfloat-abi soft \
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// RUN: -target-feature +soft-float-abi \
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// RUN: -ffreestanding \
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// RUN: -emit-llvm -w -o - %s | FileCheck %s
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#include <arm_neon.h>
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// Radar 9311427: Check that alignment specifier is used in Neon load/store
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// intrinsics.
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typedef float AlignedAddr __attribute__ ((aligned (16)));
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void t1(AlignedAddr *addr1, AlignedAddr *addr2) {
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// CHECK: @t1
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// CHECK: call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %{{.*}}, i32 16)
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float32x4_t a = vld1q_f32(addr1);
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// CHECK: call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %{{.*}}, <4 x float> %{{.*}}, i32 16)
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vst1q_f32(addr2, a);
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}
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// Radar 10538555: Make sure unaligned load/stores do not gain alignment.
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void t2(char *addr) {
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// CHECK: @t2
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// CHECK: load i32, i32* %{{.*}}, align 1
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int32x2_t vec = vld1_dup_s32(addr);
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// CHECK: store i32 %{{.*}}, i32* {{.*}}, align 1
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vst1_lane_s32(addr, vec, 1);
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}
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