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Summary: While debugging another issue, I noticed that Mips currently specifies that the count leading zero builtins are undefined when the input is zero. The architecture specifications say that the clz and dclz instructions write 32 or 64 respectively when given zero. This doesn't fix any bugs that I'm aware of but it may improve optimisation in some cases. Differential Revision: http://reviews.llvm.org/D4431 llvm-svn: 212618
33 lines
875 B
C
33 lines
875 B
C
// RUN: %clang_cc1 %s -triple mips-unknown-linux-gnu -emit-llvm -o - | FileCheck %s
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//
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// Test that the ctlz and cttz builtins are defined for zero.
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// Based on count-builtin.c
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int leading, trailing, pop;
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void test_i16(short P) {
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leading = __builtin_clzs(P);
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trailing = __builtin_ctzs(P);
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// CHECK: @test_i16
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// CHECK: call i16 @llvm.ctlz.i16(i16 {{.*}}, i1 false)
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// CHECK: call i16 @llvm.cttz.i16(i16 {{.*}}, i1 false)
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}
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void test_i32(int P) {
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leading = __builtin_clz(P);
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trailing = __builtin_ctz(P);
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// CHECK: @test_i32
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// CHECK: call i32 @llvm.ctlz.i32(i32 {{.*}}, i1 false)
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// CHECK: call i32 @llvm.cttz.i32(i32 {{.*}}, i1 false)
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}
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void test_i64(float P) {
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leading = __builtin_clzll(P);
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trailing = __builtin_ctzll(P);
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// CHECK: @test_i64
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// CHECK: call i64 @llvm.ctlz.i64(i64 {{.*}}, i1 false)
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// CHECK: call i64 @llvm.cttz.i64(i64 {{.*}}, i1 false)
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}
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