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1. Bitwise operations are used to access HwMode, allowing for the coexistence of HwMode IDs for different features (such as RegInfo and EncodingInfo). This will provide better scalability for HwMode. Currently, most users utilize HwMode primarily for configuring Register-related information, and few use it for configuring Encoding. The limited scalability of HwMode has been a significant factor in this usage pattern. 2. Sink the HwMode Encodings selection logic down to per instruction level, this makes the logic for choosing encodings clearer and provides better error messages. 3. Add some HwMode ID conflict detection to the getHwMode() interface.
163 lines
6.4 KiB
TableGen
163 lines
6.4 KiB
TableGen
// This is to test the scenario where different HwMode attributes coexist.
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// RUN: llvm-tblgen -gen-register-info -register-info-debug -I %p/../../include %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK-REG
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// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SUBTARGET
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include "llvm/Target/Target.td"
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def TestTargetInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestTargetInstrInfo;
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}
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def TestMode : HwMode<"+feat", []>;
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def TestMode1 : HwMode<"+feat1", []>;
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def TestMode2 : HwMode<"+feat2", []>;
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class MyReg<string n>
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: Register<n> {
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let Namespace = "Test";
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}
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class MyClass<int size, list<ValueType> types, dag registers>
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: RegisterClass<"Test", types, size, registers> {
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let Size = size;
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}
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def X0 : MyReg<"x0">;
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def X1 : MyReg<"x1">;
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def X2 : MyReg<"x2">;
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def X3 : MyReg<"x3">;
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def X4 : MyReg<"x4">;
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def X5 : MyReg<"x5">;
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def X6 : MyReg<"x6">;
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def X7 : MyReg<"x7">;
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def X8 : MyReg<"x8">;
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def X9 : MyReg<"x9">;
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def X10 : MyReg<"x10">;
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def X11 : MyReg<"x11">;
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def X12 : MyReg<"x12">;
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def X13 : MyReg<"x13">;
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def X14 : MyReg<"x14">;
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def X15 : MyReg<"x15">;
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def ValueModeVT : ValueTypeByHwMode<[DefaultMode, TestMode, TestMode1],
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[i32, i64, f32]>;
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let RegInfos = RegInfoByHwMode<[DefaultMode, TestMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>]> in
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def XRegs : MyClass<32, [ValueModeVT], (sequence "X%u", 0, 15)>;
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def sub_even : SubRegIndex<32> {
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let SubRegRanges = SubRegRangeByHwMode<[DefaultMode, TestMode],
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[SubRegRange<32>, SubRegRange<64>]>;
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}
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def sub_odd : SubRegIndex<32, 32> {
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let SubRegRanges = SubRegRangeByHwMode<[DefaultMode, TestMode],
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[SubRegRange<32, 32>, SubRegRange<64, 64>]>;
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}
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def XPairs : RegisterTuples<[sub_even, sub_odd],
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[(decimate (rotl XRegs, 0), 2),
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(decimate (rotl XRegs, 1), 2)]>;
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let RegInfos = RegInfoByHwMode<[DefaultMode, TestMode],
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[RegInfo<64,64,32>, RegInfo<128,128,64>]> in
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def XPairsClass : MyClass<64, [untyped], (add XPairs)>;
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// Modes who are not controlling Register related features will be manipulated
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// the same as DefaultMode.
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// CHECK-REG-LABEL: RegisterClass XRegs:
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// CHECK-REG: SpillSize: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }
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// CHECK-REG: SpillAlignment: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }
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// CHECK-REG: Regs: X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15
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// CHECK-REG-LABEL: RegisterClass XPairsClass:
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// CHECK-REG: SpillSize: { Default:64 TestMode:128 TestMode1:64 TestMode2:64 }
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// CHECK-REG: SpillAlignment: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }
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// CHECK-REG: CoveredBySubRegs: 1
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// CHECK-REG: Regs: X0_X1 X2_X3 X4_X5 X6_X7 X8_X9 X10_X11 X12_X13 X14_X15
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// CHECK-REG-LABEL: SubRegIndex sub_even:
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// CHECK-REG: Offset: { Default:0 TestMode:0 TestMode1:0 TestMode2:0 }
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// CHECK-REG: Size: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }
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// CHECK-REG-LABEL: SubRegIndex sub_odd:
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// CHECK-REG: Offset: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }
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// CHECK-REG: Size: { Default:32 TestMode:64 TestMode1:32 TestMode2:32 }
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//============================================================================//
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//--------------------- Encoding/Decoding parts ------------------------------//
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//============================================================================//
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def fooTypeEncDefault : InstructionEncoding {
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let Size = 8;
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field bits<64> SoftFail = 0;
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bits<64> Inst;
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bits<8> factor;
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let Inst{7...0} = factor;
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let Inst{3...2} = 0b10;
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let Inst{1...0} = 0b00;
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}
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def fooTypeEncA : InstructionEncoding {
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let Size = 4;
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field bits<32> SoftFail = 0;
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bits<32> Inst;
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bits<8> factor;
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let Inst{7...0} = factor;
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let Inst{3...2} = 0b11;
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let Inst{1...0} = 0b00;
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}
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def foo : Instruction {
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bits<32> Inst;
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let OutOperandList = (outs);
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let InOperandList = (ins i32imm:$factor);
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let EncodingInfos = EncodingByHwMode<
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[TestMode2, DefaultMode], [fooTypeEncA, fooTypeEncDefault]
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>;
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let AsmString = "foo $factor";
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}
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// CHECK-SUBTARGET-LABEL: unsigned TestTargetGenSubtargetInfo::getHwModeSet() const {
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// CHECK-SUBTARGET: unsigned Modes = 0;
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// CHECK-SUBTARGET: if (checkFeatures("+feat")) Modes |= (1 << 0);
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// CHECK-SUBTARGET: if (checkFeatures("+feat1")) Modes |= (1 << 1);
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// CHECK-SUBTARGET: if (checkFeatures("+feat2")) Modes |= (1 << 2);
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// CHECK-SUBTARGET: return Modes;
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// CHECK-SUBTARGET: }
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// CHECK-SUBTARGET-LABEL: unsigned TestTargetGenSubtargetInfo::getHwMode(enum HwModeType type) const {
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// CHECK-SUBTARGET: unsigned Modes = getHwModeSet();
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// CHECK-SUBTARGET: if (!Modes)
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// CHECK-SUBTARGET: return Modes;
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// CHECK-SUBTARGET: switch (type) {
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// CHECK-SUBTARGET: case HwMode_Default:
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// CHECK-SUBTARGET: return llvm::countr_zero(Modes) + 1;
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// CHECK-SUBTARGET: case HwMode_ValueType:
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// CHECK-SUBTARGET: Modes &= 3;
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// CHECK-SUBTARGET: if (!Modes)
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// CHECK-SUBTARGET: return Modes;
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// CHECK-SUBTARGET: if (!llvm::has_single_bit<unsigned>(Modes))
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// CHECK-SUBTARGET: llvm_unreachable("Two or more HwModes for ValueType were found!");
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// CHECK-SUBTARGET: return llvm::countr_zero(Modes) + 1;
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// CHECK-SUBTARGET: case HwMode_RegInfo:
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// CHECK-SUBTARGET: Modes &= 1;
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// CHECK-SUBTARGET: if (!Modes)
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// CHECK-SUBTARGET: return Modes;
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// CHECK-SUBTARGET: if (!llvm::has_single_bit<unsigned>(Modes))
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// CHECK-SUBTARGET: llvm_unreachable("Two or more HwModes for RegInfo were found!");
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// CHECK-SUBTARGET: return llvm::countr_zero(Modes) + 1;
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// CHECK-SUBTARGET: case HwMode_EncodingInfo:
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// CHECK-SUBTARGET: Modes &= 4;
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// CHECK-SUBTARGET: if (!Modes)
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// CHECK-SUBTARGET: return Modes;
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// CHECK-SUBTARGET: if (!llvm::has_single_bit<unsigned>(Modes))
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// CHECK-SUBTARGET: llvm_unreachable("Two or more HwModes for EncodingInfo were found!");
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// CHECK-SUBTARGET: return llvm::countr_zero(Modes) + 1;
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// CHECK-SUBTARGET: }
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// CHECK-SUBTARGET: llvm_unreachable("unexpected HwModeType");
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// CHECK-SUBTARGET: return 0; // should not get here
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// CHECK-SUBTARGET: }
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