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afb9c04a5a
Implement XCVbi intrinsics for CV32E40P according to the specification. This commit is part of a patch-set to upstream the 7 vendor specific extensions of CV32E40P. Contributors: @CharKeaney, @jeremybennett, @lewis-revill, @liaolucy, Nandni Jamnadas, @paolos, @simoncook, @xmj. bf2ad26b4ff856aab9a62ad168e6bdefeedc374f originally commited. e4777dc4b9cb371971523cc603e1b8a5c7255e7e reverted due to test failures caused by a merge conflict marker in llvm/test/CodeGen/RISCV/attributes that was accidentally checked in. This commit removed the conflict marker and recommitted. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D154412
927 lines
46 KiB
TableGen
927 lines
46 KiB
TableGen
//===-- RISCVFeatures.td - RISC-V Features and Extensions --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V subtarget features and instruction predicates.
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//===----------------------------------------------------------------------===//
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def FeatureStdExtZicsr
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: SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
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"'zicsr' (CSRs)">;
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def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
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AssemblerPredicate<(all_of FeatureStdExtZicsr),
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"'Zicsr' (CSRs)">;
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def FeatureStdExtM
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: SubtargetFeature<"m", "HasStdExtM", "true",
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"'M' (Integer Multiplication and Division)">;
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def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
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AssemblerPredicate<(all_of FeatureStdExtM),
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"'M' (Integer Multiplication and Division)">;
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def FeatureStdExtZmmul
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: SubtargetFeature<"zmmul", "HasStdExtZmmul", "true",
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"'Zmmul' (Integer Multiplication)">;
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def HasStdExtMOrZmmul
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: Predicate<"Subtarget->hasStdExtM() || Subtarget->hasStdExtZmmul()">,
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AssemblerPredicate<(any_of FeatureStdExtM, FeatureStdExtZmmul),
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"'M' (Integer Multiplication and Division) or "
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"'Zmmul' (Integer Multiplication)">;
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def FeatureStdExtA
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: SubtargetFeature<"a", "HasStdExtA", "true",
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"'A' (Atomic Instructions)">;
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def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
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AssemblerPredicate<(all_of FeatureStdExtA),
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"'A' (Atomic Instructions)">;
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def FeatureStdExtF
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: SubtargetFeature<"f", "HasStdExtF", "true",
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"'F' (Single-Precision Floating-Point)",
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[FeatureStdExtZicsr]>;
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def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
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AssemblerPredicate<(all_of FeatureStdExtF),
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"'F' (Single-Precision Floating-Point)">;
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def FeatureStdExtD
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: SubtargetFeature<"d", "HasStdExtD", "true",
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"'D' (Double-Precision Floating-Point)",
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[FeatureStdExtF]>;
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def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
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AssemblerPredicate<(all_of FeatureStdExtD),
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"'D' (Double-Precision Floating-Point)">;
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def FeatureStdExtH
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: SubtargetFeature<"h", "HasStdExtH", "true",
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"'H' (Hypervisor)">;
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def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,
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AssemblerPredicate<(all_of FeatureStdExtH),
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"'H' (Hypervisor)">;
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def FeatureStdExtZihintpause
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: SubtargetFeature<"zihintpause", "HasStdExtZihintpause", "true",
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"'Zihintpause' (Pause Hint)">;
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def HasStdExtZihintpause : Predicate<"Subtarget->hasStdExtZihintpause()">,
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AssemblerPredicate<(all_of FeatureStdExtZihintpause),
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"'Zihintpause' (Pause Hint)">;
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def FeatureStdExtZihintntl
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: SubtargetFeature<"experimental-zihintntl", "HasStdExtZihintntl", "true",
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"'Zihintntl' (Non-Temporal Locality Hints)">;
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def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">,
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AssemblerPredicate<(all_of FeatureStdExtZihintntl),
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"'Zihintntl' (Non-Temporal Locality Hints)">;
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def FeatureStdExtZifencei
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: SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
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"'Zifencei' (fence.i)">;
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def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
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AssemblerPredicate<(all_of FeatureStdExtZifencei),
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"'Zifencei' (fence.i)">;
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def FeatureStdExtZicntr
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: SubtargetFeature<"zicntr", "HasStdExtZicntr", "true",
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"'Zicntr' (Base Counters and Timers)",
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[FeatureStdExtZicsr]>;
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def FeatureStdExtZihpm
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: SubtargetFeature<"zihpm", "HasStdExtZihpm", "true",
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"'Zihpm' (Hardware Performance Counters)",
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[FeatureStdExtZicsr]>;
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def FeatureStdExtZfhmin
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: SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true",
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"'Zfhmin' (Half-Precision Floating-Point Minimal)",
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[FeatureStdExtF]>;
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def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
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AssemblerPredicate<(all_of FeatureStdExtZfhmin),
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"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
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def FeatureStdExtZfh
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: SubtargetFeature<"zfh", "HasStdExtZfh", "true",
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"'Zfh' (Half-Precision Floating-Point)",
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[FeatureStdExtF]>;
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def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
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AssemblerPredicate<(all_of FeatureStdExtZfh),
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"'Zfh' (Half-Precision Floating-Point)">;
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def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
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def HasStdExtZfhOrZfhmin
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: Predicate<"Subtarget->hasStdExtZfhOrZfhmin()">,
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AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin),
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"'Zfh' (Half-Precision Floating-Point) or "
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"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
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def FeatureStdExtZfinx
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: SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
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"'Zfinx' (Float in Integer)",
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[FeatureStdExtZicsr]>;
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def HasStdExtZfinx : Predicate<"Subtarget->hasStdExtZfinx()">,
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AssemblerPredicate<(all_of FeatureStdExtZfinx),
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"'Zfinx' (Float in Integer)">;
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def FeatureStdExtZdinx
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: SubtargetFeature<"zdinx", "HasStdExtZdinx", "true",
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"'Zdinx' (Double in Integer)",
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[FeatureStdExtZfinx]>;
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def HasStdExtZdinx : Predicate<"Subtarget->hasStdExtZdinx()">,
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AssemblerPredicate<(all_of FeatureStdExtZdinx),
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"'Zdinx' (Double in Integer)">;
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def FeatureStdExtZhinxmin
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: SubtargetFeature<"zhinxmin", "HasStdExtZhinxmin", "true",
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"'Zhinxmin' (Half Float in Integer Minimal)",
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[FeatureStdExtZfinx]>;
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def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
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AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
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"'Zhinxmin' (Half Float in Integer Minimal)">;
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def FeatureStdExtZhinx
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: SubtargetFeature<"zhinx", "HasStdExtZhinx", "true",
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"'Zhinx' (Half Float in Integer)",
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[FeatureStdExtZfinx]>;
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def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
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AssemblerPredicate<(all_of FeatureStdExtZhinx),
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"'Zhinx' (Half Float in Integer)">;
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def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
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def HasStdExtZhinxOrZhinxmin
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: Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
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AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin),
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"'Zhinx' (Half Float in Integer) or "
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"'Zhinxmin' (Half Float in Integer Minimal)">;
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def FeatureStdExtZfa
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: SubtargetFeature<"experimental-zfa", "HasStdExtZfa", "true",
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"'Zfa' (Additional Floating-Point)",
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[FeatureStdExtF]>;
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def HasStdExtZfa : Predicate<"Subtarget->hasStdExtZfa()">,
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AssemblerPredicate<(all_of FeatureStdExtZfa),
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"'Zfa' (Additional Floating-Point)">;
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def FeatureStdExtC
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: SubtargetFeature<"c", "HasStdExtC", "true",
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"'C' (Compressed Instructions)">;
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def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
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AssemblerPredicate<(all_of FeatureStdExtC),
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"'C' (Compressed Instructions)">;
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def FeatureStdExtZba
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: SubtargetFeature<"zba", "HasStdExtZba", "true",
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"'Zba' (Address Generation Instructions)">;
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def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">,
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AssemblerPredicate<(all_of FeatureStdExtZba),
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"'Zba' (Address Generation Instructions)">;
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def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">;
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def FeatureStdExtZbb
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: SubtargetFeature<"zbb", "HasStdExtZbb", "true",
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"'Zbb' (Basic Bit-Manipulation)">;
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def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">,
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AssemblerPredicate<(all_of FeatureStdExtZbb),
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"'Zbb' (Basic Bit-Manipulation)">;
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def FeatureStdExtZbc
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: SubtargetFeature<"zbc", "HasStdExtZbc", "true",
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"'Zbc' (Carry-Less Multiplication)">;
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def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">,
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AssemblerPredicate<(all_of FeatureStdExtZbc),
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"'Zbc' (Carry-Less Multiplication)">;
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def FeatureStdExtZbs
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: SubtargetFeature<"zbs", "HasStdExtZbs", "true",
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"'Zbs' (Single-Bit Instructions)">;
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def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
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AssemblerPredicate<(all_of FeatureStdExtZbs),
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"'Zbs' (Single-Bit Instructions)">;
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def FeatureStdExtZbkb
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: SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
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AssemblerPredicate<(all_of FeatureStdExtZbkb),
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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def FeatureStdExtZbkx
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: SubtargetFeature<"zbkx", "HasStdExtZbkx", "true",
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"'Zbkx' (Crossbar permutation instructions)">;
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def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
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AssemblerPredicate<(all_of FeatureStdExtZbkx),
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"'Zbkx' (Crossbar permutation instructions)">;
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def HasStdExtZbbOrZbkb
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: Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbkb()">,
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AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbkb),
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"'Zbb' (Basic Bit-Manipulation) or "
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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// The Carry-less multiply subextension for cryptography is a subset of basic
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// carry-less multiply subextension. The former should be enabled if the latter
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// is enabled.
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def FeatureStdExtZbkc
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: SubtargetFeature<"zbkc", "HasStdExtZbkc", "true",
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"'Zbkc' (Carry-less multiply instructions for "
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"Cryptography)">;
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def HasStdExtZbkc
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: Predicate<"Subtarget->hasStdExtZbkc()">,
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AssemblerPredicate<(all_of FeatureStdExtZbkc),
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"'Zbkc' (Carry-less multiply instructions for Cryptography)">;
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def HasStdExtZbcOrZbkc
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: Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">,
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AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc),
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"'Zbc' (Carry-Less Multiplication) or "
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"'Zbkc' (Carry-less multiply instructions "
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"for Cryptography)">;
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def FeatureStdExtZknd
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: SubtargetFeature<"zknd", "HasStdExtZknd", "true",
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"'Zknd' (NIST Suite: AES Decryption)">;
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def HasStdExtZknd : Predicate<"Subtarget->hasStdExtZknd()">,
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AssemblerPredicate<(all_of FeatureStdExtZknd),
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"'Zknd' (NIST Suite: AES Decryption)">;
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def FeatureStdExtZkne
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: SubtargetFeature<"zkne", "HasStdExtZkne", "true",
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"'Zkne' (NIST Suite: AES Encryption)">;
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def HasStdExtZkne : Predicate<"Subtarget->hasStdExtZkne()">,
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AssemblerPredicate<(all_of FeatureStdExtZkne),
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"'Zkne' (NIST Suite: AES Encryption)">;
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// Some instructions belong to both Zknd and Zkne subextensions.
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// They should be enabled if either has been specified.
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def HasStdExtZkndOrZkne
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: Predicate<"Subtarget->hasStdExtZknd() || Subtarget->hasStdExtZkne()">,
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AssemblerPredicate<(any_of FeatureStdExtZknd, FeatureStdExtZkne),
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"'Zknd' (NIST Suite: AES Decryption) or "
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"'Zkne' (NIST Suite: AES Encryption)">;
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def FeatureStdExtZknh
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: SubtargetFeature<"zknh", "HasStdExtZknh", "true",
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"'Zknh' (NIST Suite: Hash Function Instructions)">;
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def HasStdExtZknh : Predicate<"Subtarget->hasStdExtZknh()">,
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AssemblerPredicate<(all_of FeatureStdExtZknh),
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"'Zknh' (NIST Suite: Hash Function Instructions)">;
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def FeatureStdExtZksed
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: SubtargetFeature<"zksed", "HasStdExtZksed", "true",
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"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
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def HasStdExtZksed : Predicate<"Subtarget->hasStdExtZksed()">,
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AssemblerPredicate<(all_of FeatureStdExtZksed),
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"'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)">;
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def FeatureStdExtZksh
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: SubtargetFeature<"zksh", "HasStdExtZksh", "true",
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"'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)">;
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def HasStdExtZksh : Predicate<"Subtarget->hasStdExtZksh()">,
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AssemblerPredicate<(all_of FeatureStdExtZksh),
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"'Zksh' (ShangMi Suite: SM3 Hash Function "
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"Instructions)">;
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def FeatureStdExtZkr
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: SubtargetFeature<"zkr", "HasStdExtZkr", "true",
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"'Zkr' (Entropy Source Extension)">;
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def HasStdExtZkr : Predicate<"Subtarget->hasStdExtZkr()">,
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AssemblerPredicate<(all_of FeatureStdExtZkr),
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"'Zkr' (Entropy Source Extension)">;
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def FeatureStdExtZkn
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: SubtargetFeature<"zkn", "HasStdExtZkn", "true",
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"'Zkn' (NIST Algorithm Suite)",
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[FeatureStdExtZbkb,
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FeatureStdExtZbkc,
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FeatureStdExtZbkx,
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FeatureStdExtZkne,
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FeatureStdExtZknd,
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FeatureStdExtZknh]>;
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def FeatureStdExtZks
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: SubtargetFeature<"zks", "HasStdExtZks", "true",
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"'Zks' (ShangMi Algorithm Suite)",
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[FeatureStdExtZbkb,
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FeatureStdExtZbkc,
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FeatureStdExtZbkx,
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FeatureStdExtZksed,
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FeatureStdExtZksh]>;
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def FeatureStdExtZkt
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: SubtargetFeature<"zkt", "HasStdExtZkt", "true",
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"'Zkt' (Data Independent Execution Latency)">;
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def FeatureStdExtZk
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: SubtargetFeature<"zk", "HasStdExtZk", "true",
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"'Zk' (Standard scalar cryptography extension)",
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[FeatureStdExtZkn,
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FeatureStdExtZkr,
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FeatureStdExtZkt]>;
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def FeatureStdExtZca
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: SubtargetFeature<"zca", "HasStdExtZca", "true",
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"'Zca' (part of the C extension, excluding compressed "
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"floating point loads/stores)">;
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def HasStdExtCOrZca
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: Predicate<"Subtarget->hasStdExtCOrZca()">,
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AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZca),
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"'C' (Compressed Instructions) or "
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"'Zca' (part of the C extension, excluding "
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"compressed floating point loads/stores)">;
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def FeatureStdExtZcb
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: SubtargetFeature<"zcb", "HasStdExtZcb", "true",
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"'Zcb' (Compressed basic bit manipulation instructions)",
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[FeatureStdExtZca]>;
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def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">,
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AssemblerPredicate<(all_of FeatureStdExtZcb),
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"'Zcb' (Compressed basic bit manipulation instructions)">;
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def FeatureStdExtZcd
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: SubtargetFeature<"zcd", "HasStdExtZcd", "true",
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"'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
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[FeatureStdExtZca]>;
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def HasStdExtCOrZcd
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: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">,
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AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcd),
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"'C' (Compressed Instructions) or "
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"'Zcd' (Compressed Double-Precision Floating-Point Instructions)">;
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def FeatureStdExtZcf
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: SubtargetFeature<"zcf", "HasStdExtZcf", "true",
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"'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
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[FeatureStdExtZca]>;
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def FeatureStdExtZcmp
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: SubtargetFeature<"zcmp", "HasStdExtZcmp", "true",
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"'Zcmp' (sequenced instuctions for code-size reduction)",
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[FeatureStdExtZca]>;
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def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
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AssemblerPredicate<(all_of FeatureStdExtZcmp),
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"'Zcmp' (sequenced instuctions for code-size reduction)">;
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def FeatureStdExtZcmt
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: SubtargetFeature<"zcmt", "HasStdExtZcmt", "true",
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"'Zcmt' (table jump instuctions for code-size reduction)",
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[FeatureStdExtZca, FeatureStdExtZicsr]>;
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def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
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AssemblerPredicate<(all_of FeatureStdExtZcmt),
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"'Zcmt' (table jump instuctions for code-size reduction)">;
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def FeatureStdExtZce
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: SubtargetFeature<"zce", "HasStdExtZce", "true",
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"'Zce' (Compressed extensions for microcontrollers)",
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[FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp,
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FeatureStdExtZcmt]>;
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def HasStdExtCOrZcfOrZce
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: Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() "
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"Subtarget->hasStdExtZce()">,
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AssemblerPredicate<(any_of FeatureStdExtC, FeatureStdExtZcf,
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FeatureStdExtZce),
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"'C' (Compressed Instructions) or "
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"'Zcf' (Compressed Single-Precision Floating-Point Instructions)">;
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def FeatureNoRVCHints
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: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
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"Disable RVC Hint Instructions.">;
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def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
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|
AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
|
|
"RVC Hint Instructions">;
|
|
|
|
def FeatureStdExtZvl32b : SubtargetFeature<"zvl32b", "ZvlLen", "32",
|
|
"'Zvl' (Minimum Vector Length) 32">;
|
|
|
|
foreach i = { 6-16 } in {
|
|
defvar I = !shl(1, i);
|
|
def FeatureStdExtZvl#I#b :
|
|
SubtargetFeature<"zvl"#I#"b", "ZvlLen", !cast<string>(I),
|
|
"'Zvl' (Minimum Vector Length) "#I,
|
|
[!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
|
|
}
|
|
|
|
def FeatureStdExtZve32x
|
|
: SubtargetFeature<"zve32x", "HasStdExtZve32x", "true",
|
|
"'Zve32x' (Vector Extensions for Embedded Processors "
|
|
"with maximal 32 EEW)",
|
|
[FeatureStdExtZicsr, FeatureStdExtZvl32b]>;
|
|
|
|
def FeatureStdExtZve32f
|
|
: SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
|
|
"'Zve32f' (Vector Extensions for Embedded Processors "
|
|
"with maximal 32 EEW and F extension)",
|
|
[FeatureStdExtZve32x, FeatureStdExtF]>;
|
|
|
|
def FeatureStdExtZve64x
|
|
: SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
|
|
"'Zve64x' (Vector Extensions for Embedded Processors "
|
|
"with maximal 64 EEW)",
|
|
[FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
|
|
|
|
def FeatureStdExtZve64f
|
|
: SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
|
|
"'Zve64f' (Vector Extensions for Embedded Processors "
|
|
"with maximal 64 EEW and F extension)",
|
|
[FeatureStdExtZve32f, FeatureStdExtZve64x]>;
|
|
|
|
def FeatureStdExtZve64d
|
|
: SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
|
|
"'Zve64d' (Vector Extensions for Embedded Processors "
|
|
"with maximal 64 EEW, F and D extension)",
|
|
[FeatureStdExtZve64f, FeatureStdExtD]>;
|
|
|
|
def FeatureStdExtV
|
|
: SubtargetFeature<"v", "HasStdExtV", "true",
|
|
"'V' (Vector Extension for Application Processors)",
|
|
[FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
|
|
|
|
def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,
|
|
AssemblerPredicate<
|
|
(any_of FeatureStdExtZve32x),
|
|
"'V' (Vector Extension for Application Processors), 'Zve32x' or "
|
|
"'Zve64x' (Vector Extensions for Embedded Processors)">;
|
|
def HasVInstructionsI64 : Predicate<"Subtarget->hasVInstructionsI64()">,
|
|
AssemblerPredicate<
|
|
(any_of FeatureStdExtZve64x),
|
|
"'V' (Vector Extension for Application Processors) or 'Zve64x' "
|
|
"(Vector Extensions for Embedded Processors)">;
|
|
def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">,
|
|
AssemblerPredicate<
|
|
(any_of FeatureStdExtZve32f),
|
|
"'V' (Vector Extension for Application Processors), 'Zve32f', "
|
|
"'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">;
|
|
|
|
def HasVInstructionsF64 : Predicate<"Subtarget->hasVInstructionsF64()">;
|
|
|
|
def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">;
|
|
|
|
def FeatureStdExtZfbfmin
|
|
: SubtargetFeature<"experimental-zfbfmin", "HasStdExtZfbfmin", "true",
|
|
"'Zfbfmin' (Scalar BF16 Converts)",
|
|
[FeatureStdExtF]>;
|
|
def HasStdExtZfbfmin : Predicate<"Subtarget->hasStdExtZfbfmin()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZfbfmin),
|
|
"'Zfbfmin' (Scalar BF16 Converts)">;
|
|
|
|
def FeatureStdExtZvfbfmin
|
|
: SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true",
|
|
"'Zvbfmin' (Vector BF16 Converts)",
|
|
[FeatureStdExtZve32f, FeatureStdExtZfbfmin]>;
|
|
def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZvfbfmin),
|
|
"'Zvfbfmin' (Vector BF16 Converts)">;
|
|
|
|
def FeatureStdExtZvfbfwma
|
|
: SubtargetFeature<"experimental-zvfbfwma", "HasStdExtZvfbfwma", "true",
|
|
"'Zvfbfwma' (Vector BF16 widening mul-add)",
|
|
[FeatureStdExtZvfbfmin]>;
|
|
def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZvfbfwma),
|
|
"'Zvfbfwma' (Vector BF16 widening mul-add)">;
|
|
|
|
def HasVInstructionsBF16 : Predicate<"Subtarget->hasVInstructionsBF16()">;
|
|
|
|
def FeatureStdExtZvfh
|
|
: SubtargetFeature<"zvfh", "HasStdExtZvfh", "true",
|
|
"'Zvfh' (Vector Half-Precision Floating-Point)",
|
|
[FeatureStdExtZve32f, FeatureStdExtZfhmin]>;
|
|
|
|
def HasVInstructionsF16 : Predicate<"Subtarget->hasVInstructionsF16()">;
|
|
|
|
def HasStdExtZfhOrZvfh
|
|
: Predicate<"Subtarget->hasStdExtZfh() || Subtarget->hasStdExtZvfh()">,
|
|
AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZvfh),
|
|
"'Zfh' (Half-Precision Floating-Point) or "
|
|
"'Zvfh' (Vector Half-Precision Floating-Point)">;
|
|
|
|
def FeatureStdExtZicbom
|
|
: SubtargetFeature<"zicbom", "HasStdExtZicbom", "true",
|
|
"'Zicbom' (Cache-Block Management Instructions)">;
|
|
def HasStdExtZicbom : Predicate<"Subtarget->hasStdExtZicbom()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZicbom),
|
|
"'Zicbom' (Cache-Block Management Instructions)">;
|
|
|
|
def FeatureStdExtZicboz
|
|
: SubtargetFeature<"zicboz", "HasStdExtZicboz", "true",
|
|
"'Zicboz' (Cache-Block Zero Instructions)">;
|
|
def HasStdExtZicboz : Predicate<"Subtarget->hasStdExtZicboz()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZicboz),
|
|
"'Zicboz' (Cache-Block Zero Instructions)">;
|
|
|
|
def FeatureStdExtZicbop
|
|
: SubtargetFeature<"zicbop", "HasStdExtZicbop", "true",
|
|
"'Zicbop' (Cache-Block Prefetch Instructions)">;
|
|
def HasStdExtZicbop : Predicate<"Subtarget->hasStdExtZicbop()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZicbop),
|
|
"'Zicbop' (Cache-Block Prefetch Instructions)">;
|
|
|
|
def FeatureStdExtSvnapot
|
|
: SubtargetFeature<"svnapot", "HasStdExtSvnapot", "true",
|
|
"'Svnapot' (NAPOT Translation Contiguity)">;
|
|
|
|
def FeatureStdExtSvpbmt
|
|
: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
|
|
"'Svpbmt' (Page-Based Memory Types)">;
|
|
|
|
def FeatureStdExtSvinval
|
|
: SubtargetFeature<"svinval", "HasStdExtSvinval", "true",
|
|
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
|
|
def HasStdExtSvinval : Predicate<"Subtarget->hasStdExtSvinval()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtSvinval),
|
|
"'Svinval' (Fine-Grained Address-Translation Cache Invalidation)">;
|
|
|
|
def FeatureStdExtZtso
|
|
: SubtargetFeature<"experimental-ztso", "HasStdExtZtso", "true",
|
|
"'Ztso' (Memory Model - Total Store Order)">;
|
|
def HasStdExtZtso : Predicate<"Subtarget->hasStdExtZTso()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZtso),
|
|
"'Ztso' (Memory Model - Total Store Order)">;
|
|
|
|
def FeatureStdExtZawrs : SubtargetFeature<"zawrs", "HasStdExtZawrs", "true",
|
|
"'Zawrs' (Wait on Reservation Set)">;
|
|
def HasStdExtZawrs : Predicate<"Subtarget->hasStdExtZawrs()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZawrs),
|
|
"'Zawrs' (Wait on Reservation Set)">;
|
|
|
|
def FeatureStdExtZvbb
|
|
: SubtargetFeature<"experimental-zvbb", "HasStdExtZvbb", "true",
|
|
"'Zvbb' (Vector Bit-manipulation used in Cryptography)">;
|
|
def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZvbb),
|
|
"'Zvbb' (Vector Bit-manipulation used in Cryptography)">;
|
|
|
|
def FeatureStdExtZvbc
|
|
: SubtargetFeature<"experimental-zvbc", "HasStdExtZvbc", "true",
|
|
"'Zvbc' (Vector Carryless Multiplication)">;
|
|
def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZvbc),
|
|
"'Zvbc' (Vector Carryless Multiplication)">;
|
|
|
|
def FeatureStdExtZvkg
|
|
: SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true",
|
|
"'Zvkg' (Vector GCM instructions for Cryptography)">;
|
|
def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZvkg),
|
|
"'Zvkg' (Vector GCM instructions for Cryptography)">;
|
|
|
|
def FeatureStdExtZvkned
|
|
: SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true",
|
|
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
|
|
def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZvkned),
|
|
"'Zvkned' (Vector AES Encryption & Decryption (Single Round))">;
|
|
|
|
def FeatureStdExtZvknha
|
|
: SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true",
|
|
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
|
|
|
|
def FeatureStdExtZvknhb
|
|
: SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true",
|
|
"'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
|
|
[FeatureStdExtZvknha]>;
|
|
def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZvknha),
|
|
"'Zvknha' (Vector SHA-2 (SHA-256 only))">;
|
|
|
|
def FeatureStdExtZvksed
|
|
: SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true",
|
|
"'Zvksed' (SM4 Block Cipher Instructions)">;
|
|
def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZvksed),
|
|
"'Zvksed' (SM4 Block Cipher Instructions)">;
|
|
|
|
def FeatureStdExtZvksh
|
|
: SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true",
|
|
"'Zvksh' (SM3 Hash Function Instructions)">;
|
|
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZvksh),
|
|
"'Zvksh' (SM3 Hash Function Instructions)">;
|
|
|
|
def FeatureStdExtZvkt
|
|
: SubtargetFeature<"experimental-zvkt", "HasStdExtZvkt", "true",
|
|
"'Zvkt' (Vector Data-Independent Execution Latency)">;
|
|
|
|
// Zvk short-hand extensions
|
|
|
|
def FeatureStdExtZvkn
|
|
: SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true",
|
|
"This extension is shorthand for the following set of "
|
|
"other extensions: Zvkned, Zvknhb, Zvbb and Zvkt.",
|
|
[FeatureStdExtZvkned, FeatureStdExtZvknhb,
|
|
FeatureStdExtZvbb, FeatureStdExtZvkt]>;
|
|
|
|
def FeatureStdExtZvknc
|
|
: SubtargetFeature<"experimental-zvknc", "HasStdExtZvknc", "true",
|
|
"This extension is shorthand for the following set of "
|
|
"other extensions: Zvkn and Zvbc.",
|
|
[FeatureStdExtZvkn, FeatureStdExtZvbc]>;
|
|
|
|
def FeatureStdExtZvkng
|
|
: SubtargetFeature<"experimental-zvkng", "HasStdExtZvkng", "true",
|
|
"This extension is shorthand for the following set of "
|
|
"other extensions: Zvkn and Zvkg.",
|
|
[FeatureStdExtZvkn, FeatureStdExtZvkg]>;
|
|
|
|
def FeatureStdExtZvks
|
|
: SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true",
|
|
"This extension is shorthand for the following set of "
|
|
"other extensions: Zvksed, Zvksh, Zvbb and Zvkt.",
|
|
[FeatureStdExtZvksed, FeatureStdExtZvksh,
|
|
FeatureStdExtZvbb, FeatureStdExtZvkt]>;
|
|
|
|
def FeatureStdExtZvksc
|
|
: SubtargetFeature<"experimental-zvksc", "HasStdExtZvksc", "true",
|
|
"This extension is shorthand for the following set of "
|
|
"other extensions: Zvks and Zvbc.",
|
|
[FeatureStdExtZvks, FeatureStdExtZvbc]>;
|
|
|
|
def FeatureStdExtZvksg
|
|
: SubtargetFeature<"experimental-zvksg", "HasStdExtZvksg", "true",
|
|
"This extension is shorthand for the following set of "
|
|
"other extensions: Zvks and Zvkg.",
|
|
[FeatureStdExtZvks, FeatureStdExtZvkg]>;
|
|
|
|
def FeatureStdExtZicond
|
|
: SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
|
|
"'Zicond' (Integer Conditional Operations)">;
|
|
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZicond),
|
|
"'Zicond' (Integer Conditional Operations)">;
|
|
|
|
def FeatureStdExtSmaia
|
|
: SubtargetFeature<"experimental-smaia", "HasStdExtSmaia", "true",
|
|
"'Smaia' (Smaia encompasses all added CSRs and all "
|
|
"modifications to interrupt response behavior that the "
|
|
"AIA specifies for a hart, over all privilege levels.)",
|
|
[]>;
|
|
|
|
def FeatureStdExtSsaia
|
|
: SubtargetFeature<"experimental-ssaia", "HasStdExtSsaia", "true",
|
|
"'Ssaia' (Ssaia is essentially the same as Smaia except "
|
|
"excluding the machine-level CSRs and behavior not "
|
|
"directly visible to supervisor level.)", []>;
|
|
|
|
def HasHalfFPLoadStoreMove
|
|
: Predicate<"Subtarget->hasHalfFPLoadStoreMove()">,
|
|
AssemblerPredicate<(any_of FeatureStdExtZfh, FeatureStdExtZfhmin,
|
|
FeatureStdExtZfbfmin),
|
|
"'Zfh' (Half-Precision Floating-Point) or "
|
|
"'Zfhmin' (Half-Precision Floating-Point Minimal) or "
|
|
"'Zfbfmin' (Scalar BF16 Converts)">;
|
|
|
|
def FeatureStdExtZacas
|
|
: SubtargetFeature<"experimental-zacas", "HasStdExtZacas", "true",
|
|
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
|
|
def HasStdExtZacas : Predicate<"Subtarget->hasStdExtZacas()">,
|
|
AssemblerPredicate<(all_of FeatureStdExtZacas),
|
|
"'Zacas' (Atomic Compare-And-Swap Instructions)">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Vendor extensions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def FeatureVendorXVentanaCondOps
|
|
: SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
|
|
"'XVentanaCondOps' (Ventana Conditional Ops)">;
|
|
def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXVentanaCondOps),
|
|
"'XVentanaCondOps' (Ventana Conditional Ops)">;
|
|
|
|
def FeatureVendorXTHeadBa
|
|
: SubtargetFeature<"xtheadba", "HasVendorXTHeadBa", "true",
|
|
"'xtheadba' (T-Head address calculation instructions)">;
|
|
def HasVendorXTHeadBa : Predicate<"Subtarget->hasVendorXTHeadBa()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadBa),
|
|
"'xtheadba' (T-Head address calculation instructions)">;
|
|
|
|
def FeatureVendorXTHeadBb
|
|
: SubtargetFeature<"xtheadbb", "HasVendorXTHeadBb", "true",
|
|
"'xtheadbb' (T-Head basic bit-manipulation instructions)">;
|
|
def HasVendorXTHeadBb : Predicate<"Subtarget->hasVendorXTHeadBb()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadBb),
|
|
"'xtheadbb' (T-Head basic bit-manipulation instructions)">;
|
|
|
|
def FeatureVendorXTHeadBs
|
|
: SubtargetFeature<"xtheadbs", "HasVendorXTHeadBs", "true",
|
|
"'xtheadbs' (T-Head single-bit instructions)">;
|
|
def HasVendorXTHeadBs : Predicate<"Subtarget->hasVendorXTHeadBs()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadBs),
|
|
"'xtheadbs' (T-Head single-bit instructions)">;
|
|
|
|
def FeatureVendorXTHeadCondMov
|
|
: SubtargetFeature<"xtheadcondmov", "HasVendorXTHeadCondMov", "true",
|
|
"'xtheadcondmov' (T-Head conditional move instructions)">;
|
|
def HasVendorXTHeadCondMov : Predicate<"Subtarget->hasVendorXTHeadCondMov()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadCondMov),
|
|
"'xtheadcondmov' (T-Head conditional move instructions)">;
|
|
|
|
def FeatureVendorXTHeadCmo
|
|
: SubtargetFeature<"xtheadcmo", "HasVendorXTHeadCmo", "true",
|
|
"'xtheadcmo' (T-Head cache management instructions)">;
|
|
def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadCmo),
|
|
"'xtheadcmo' (T-Head cache management instructions)">;
|
|
|
|
def FeatureVendorXTHeadFMemIdx
|
|
: SubtargetFeature<"xtheadfmemidx", "HasVendorXTHeadFMemIdx", "true",
|
|
"'xtheadfmemidx' (T-Head FP Indexed Memory Operations)",
|
|
[FeatureStdExtF]>;
|
|
def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx),
|
|
"'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">;
|
|
|
|
def FeatureVendorXTHeadMac
|
|
: SubtargetFeature<"xtheadmac", "HasVendorXTHeadMac", "true",
|
|
"'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
|
|
def HasVendorXTHeadMac : Predicate<"Subtarget->hasVendorXTHeadMac()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadMac),
|
|
"'xtheadmac' (T-Head Multiply-Accumulate Instructions)">;
|
|
|
|
def FeatureVendorXTHeadMemIdx
|
|
: SubtargetFeature<"xtheadmemidx", "HasVendorXTHeadMemIdx", "true",
|
|
"'xtheadmemidx' (T-Head Indexed Memory Operations)">;
|
|
def HasVendorXTHeadMemIdx : Predicate<"Subtarget->hasVendorXTHeadMemIdx()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadMemIdx),
|
|
"'xtheadmemidx' (T-Head Indexed Memory Operations)">;
|
|
|
|
def FeatureVendorXTHeadMemPair
|
|
: SubtargetFeature<"xtheadmempair", "HasVendorXTHeadMemPair", "true",
|
|
"'xtheadmempair' (T-Head two-GPR Memory Operations)">;
|
|
def HasVendorXTHeadMemPair : Predicate<"Subtarget->hasVendorXTHeadMemPair()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadMemPair),
|
|
"'xtheadmempair' (T-Head two-GPR Memory Operations)">;
|
|
|
|
def FeatureVendorXTHeadSync
|
|
: SubtargetFeature<"xtheadsync", "HasVendorXTHeadSync", "true",
|
|
"'xtheadsync' (T-Head multicore synchronization instructions)">;
|
|
def HasVendorXTHeadSync : Predicate<"Subtarget->hasVendorXTHeadSync()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadSync),
|
|
"'xtheadsync' (T-Head multicore synchronization instructions)">;
|
|
|
|
def FeatureVendorXTHeadVdot
|
|
: SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
|
|
"'xtheadvdot' (T-Head Vector Extensions for Dot)",
|
|
[FeatureStdExtV]>;
|
|
def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
|
|
"'xtheadvdot' (T-Head Vector Extensions for Dot)">;
|
|
|
|
def FeatureVendorXSfvcp
|
|
: SubtargetFeature<"xsfvcp", "HasVendorXSfvcp", "true",
|
|
"'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)",
|
|
[FeatureStdExtZve32x]>;
|
|
def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXSfvcp),
|
|
"'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)">;
|
|
|
|
def FeatureVendorXSfcie
|
|
: SubtargetFeature<"xsfcie", "HasVendorXSfcie", "true",
|
|
"'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
|
|
def HasVendorXSfcie : Predicate<"Subtarget->hasVendorXSfcie()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXSfcie),
|
|
"'XSfcie' (SiFive Custom Instruction Extension SCIE.)">;
|
|
|
|
def FeatureVendorXCVbitmanip
|
|
: SubtargetFeature<"xcvbitmanip", "HasVendorXCVbitmanip", "true",
|
|
"'XCVbitmanip' (CORE-V Bit Manipulation)">;
|
|
def HasVendorXCVbitmanip : Predicate<"Subtarget->hasVendorXCVbitmanip()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXCVbitmanip),
|
|
"'XCVbitmanip' (CORE-V Bit Manipulation)">;
|
|
|
|
def FeatureVendorXCVmac
|
|
: SubtargetFeature<"xcvmac", "HasVendorXCVmac", "true",
|
|
"'XCVmac' (CORE-V Multiply-Accumulate)">;
|
|
def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXCVmac),
|
|
"'XCVmac' (CORE-V Multiply-Accumulate)">;
|
|
|
|
def FeatureVendorXCValu
|
|
: SubtargetFeature<"xcvalu", "HasVendorXCValu", "true",
|
|
"'XCValu' (CORE-V ALU Operations)">;
|
|
def HasVendorXCValu : Predicate<"Subtarget->hasVendorXCValu()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXCValu),
|
|
"'XCValu' (CORE-V ALU Operations)">;
|
|
|
|
def FeatureVendorXCVsimd
|
|
: SubtargetFeature<"xcvsimd", "HasVendorXCvsimd", "true",
|
|
"'XCVsimd' (CORE-V SIMD ALU)">;
|
|
def HasVendorXCVsimd
|
|
: Predicate<"Subtarget->hasVendorXCVsimd()">,
|
|
AssemblerPredicate<(any_of FeatureVendorXCVsimd),
|
|
"'XCVsimd' (CORE-V SIMD ALU)">;
|
|
|
|
def FeatureVendorXCVbi
|
|
: SubtargetFeature<"xcvbi", "HasVendorXCVbi", "true",
|
|
"'XCVbi' (CORE-V Immediate Branching)">;
|
|
def HasVendorXCVbi : Predicate<"Subtarget->hasVendorXCVbi()">,
|
|
AssemblerPredicate<(all_of FeatureVendorXCVbi),
|
|
"'XCVbi' (CORE-V Immediate Branching)">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// LLVM specific features and extensions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
|
|
// tuning CPU names.
|
|
def Feature32Bit
|
|
: SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
|
|
def Feature64Bit
|
|
: SubtargetFeature<"64bit", "IsRV64", "true", "Implements RV64">;
|
|
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
|
|
AssemblerPredicate<(all_of Feature64Bit),
|
|
"RV64I Base Instruction Set">;
|
|
def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
|
|
AssemblerPredicate<(all_of (not Feature64Bit)),
|
|
"RV32I Base Instruction Set">;
|
|
|
|
defvar RV32 = DefaultMode;
|
|
def RV64 : HwMode<"+64bit", [IsRV64]>;
|
|
|
|
def FeatureRVE
|
|
: SubtargetFeature<"e", "IsRVE", "true",
|
|
"Implements RV{32,64}E (provides 16 rather than 32 GPRs)">;
|
|
def IsRVE : Predicate<"Subtarget->isRVE()">,
|
|
AssemblerPredicate<(all_of FeatureRVE)>;
|
|
|
|
def FeatureRelax
|
|
: SubtargetFeature<"relax", "EnableLinkerRelax", "true",
|
|
"Enable Linker relaxation.">;
|
|
|
|
foreach i = {1-31} in
|
|
def FeatureReserveX#i :
|
|
SubtargetFeature<"reserve-x"#i, "UserReservedRegister[RISCV::X"#i#"]",
|
|
"true", "Reserve X"#i>;
|
|
|
|
def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
|
|
"true", "Enable save/restore.">;
|
|
|
|
def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence",
|
|
"EnableSeqCstTrailingFence",
|
|
"true",
|
|
"Enable trailing fence for seq-cst store.">;
|
|
|
|
def FeatureUnalignedScalarMem
|
|
: SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
|
|
"true", "Has reasonably performant unaligned scalar "
|
|
"loads and stores">;
|
|
|
|
def FeatureUnalignedVectorMem
|
|
: SubtargetFeature<"unaligned-vector-mem", "EnableUnalignedVectorMem",
|
|
"true", "Has reasonably performant unaligned vector "
|
|
"loads and stores">;
|
|
|
|
def TuneNoOptimizedZeroStrideLoad
|
|
: SubtargetFeature<"no-optimized-zero-stride-load", "HasOptimizedZeroStrideLoad",
|
|
"false", "Hasn't optimized (perform fewer memory operations)"
|
|
"zero-stride vector load">;
|
|
|
|
// Some vector hardware implementations do not process all VLEN bits in parallel
|
|
// and instead split over multiple cycles. DLEN refers to the datapath width
|
|
// that can be done in parallel.
|
|
def TuneDLenFactor2
|
|
: SubtargetFeature<"dlen-factor-2", "DLenFactor2", "true",
|
|
"Vector unit DLEN(data path width) is half of VLEN">;
|
|
|
|
def TuneLUIADDIFusion
|
|
: SubtargetFeature<"lui-addi-fusion", "HasLUIADDIFusion",
|
|
"true", "Enable LUI+ADDI macrofusion">;
|
|
|
|
def TuneNoDefaultUnroll
|
|
: SubtargetFeature<"no-default-unroll", "EnableDefaultUnroll", "false",
|
|
"Disable default unroll preference.">;
|
|
|
|
// SiFive 7 is able to fuse integer ALU operations with a preceding branch
|
|
// instruction.
|
|
def TuneShortForwardBranchOpt
|
|
: SubtargetFeature<"short-forward-branch-opt", "HasShortForwardBranchOpt",
|
|
"true", "Enable short forward branch optimization">;
|
|
def HasShortForwardBranchOpt : Predicate<"Subtarget->hasShortForwardBranchOpt()">;
|
|
def NoShortForwardBranchOpt : Predicate<"!Subtarget->hasShortForwardBranchOpt()">;
|
|
|
|
def TuneSiFive7 : SubtargetFeature<"sifive7", "RISCVProcFamily", "SiFive7",
|
|
"SiFive 7-Series processors",
|
|
[TuneNoDefaultUnroll,
|
|
TuneShortForwardBranchOpt]>;
|
|
|
|
// Assume that lock-free native-width atomics are available, even if the target
|
|
// and operating system combination would not usually provide them. The user
|
|
// is responsible for providing any necessary __sync implementations. Code
|
|
// built with this feature is not ABI-compatible with code built without this
|
|
// feature, if atomic variables are exposed across the ABI boundary.
|
|
def FeatureForcedAtomics : SubtargetFeature<
|
|
"forced-atomics", "HasForcedAtomics", "true",
|
|
"Assume that lock-free native-width atomics are available">;
|
|
def HasAtomicLdSt
|
|
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
|
|
|
|
def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
|
|
"AllowTaggedGlobals",
|
|
"true", "Use an instruction sequence for taking the address of a global "
|
|
"that allows a memory tag in the upper address bits">;
|